Phase Interpolation Research Articles

A 12-GHz Calibration-Free All-Digital PLL for FMCW Signal Generation With 78 MHz/μs Chirp Slope and High Chirp Linearity

A novel all-digital phase-locked loop (ADPLL) for fast and high-linear FMCW signal generation is presented in this paper. Fast chirp slope is enabled by two-point modulation (TPM) technique and ramp linearity distortion induced by digitally- controlled oscillator (DCO) is suppressed by wide loop bandwidth. A calibration-free retiming fractional frequency dividing (FFD) scheme based on digital phase interpolator (DPI) is proposed to suppress the $\Delta \Sigma $ quantization noise and break the loop bandwidth limitation. A parasitic insensitive DPI is utilized in the retiming FFD scheme to achieve high-linear phase interpolation. A high frequency resolution DCO with 9.8-kHz/bit least significant bit (LSB) and a vernier time-to-digital convertor (TDC) with 2.3-ps time resolution are employed to further minimize the quantization noise. Implemented in 40-nm CMOS, the ADPLL prototype consumes 33.8 mW power and 0.32 mm2 chip area. Measurement results show that 78 MHz/ $\mu \text{s}$ maximum chirp slope is achieved with 167 kHz root-mean-square (RMS) frequency error. The minimum RMS frequency error is only 5.6 kHz when 300 MHz frequency is swept in 1 ms. The phase noise from 12.15 GHz carrier is −113.6 dBc/Hz at 1-MHz offset.

Synthesisable glitch‐less phase rotator with conditionally cascading scheme

This Letter presents a synthesisable phase rotator (PR) which operates without switching glitches that are reported in conventional implementations. The proposed conditionally cascading PR (CCPR) is comprised of two multiplexers (MUXes) with logic gates, and a phase interpolator (PI). This composition enables the automatic design flow through hardware description language which shortens the design time. With the MUXes operating as a cascaded PI at transition points, the proposed CCPR outputs a clock without any transient anomaly. A remarkable reduction in power and area is achieved by sharing a common PI for every pair of input clocks and merging low pass filters into the MUXes. Simulated in a 40-nm technology, the proposed CCPR consumes 1.9 mW at a 1.1 V supply with 5.4 GHz operation.

A 32-Step Phase-Compensated Spread-Spectrum RF-PLL With 19.44-dB EMI Reduction and 10-fs Extra RMS Jitter

Spread-spectrum clocking (SSC) is an active solution to attenuate electromagnetic interference (EMI) in Gb/s serial communication systems by slightly modulating the phase-locked loop (PLL) output clock frequency. This article presents a phase-compensated spread-spectrum clock generator (SSCG) with the state-of-the-art EMI reduction and clock rms jitter performance. A 32-slice scaled resistor-based buffer is proposed to realize the phase interpolator (PI). The proposed design has no static current and low complexity without active device matching requirement. The 32-slice PI structure can achieve a simulated 22-dB EMI reduction with a 32-step triangular modulation profile. The proposed SSCG chip with a charge-pump-based fractional- $N$ radio frequency (RF)-PLL and a source-series-terminated (SST) driver is fabricated using a 55-nm CMOS process. Measurement result shows that EMI reduction of the 5-GHz output clock power spectrum is 19.44 dB under 0.5% down-spread. The rms jitters with SSC-off and SSC-on, adopting a second-order clock recovery in oscilloscope, are 630 and 640 fs, respectively. The normalized power consumption is 9.3 mW/GHz, and the core area occupation is 0.092 mm2.

A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications

In an effort to keep pace with bandwidth growth, DRAM employes the quad data rate (QDR) to transfer four data in one clock cycle. In recent graphic memories, QDR is being implemented by a phase-locked loop (PLL). However, it is hard to apply a PLL to main and mobile memories for its high power dissipation and hardware cost. Therefore, we propose a new delay-locked loop-based quadrature clock generator (DLL-QCG) to replace a PLL. A sub-range technique is adopted for a phase interpolator (PI) to achieve a very fine resolution with low power and small area. A tiny resolution mitigates the jitter accumulation effect of the conventional all-digital DLL-QCG and reduces a phase error. With the introduction of the sub-range PI, the delay line structure is changed from two-stage (coarse-fine) to three-stage (coarse-fine-finer). To control this, we also develop a new controller, which ensures clock quality through seamless boundary switching at the fine-to-finer. The circuit is fabricated using a 28 nm CMOS FDSOI technology with a 1 V supply voltage and an area of 0.0072 mm2. It operates from 1.8 to 2.5 GHz and achieves a phase error of 3.35° to 6.35° without a quadrature-phase collector. In addition, the measured RMS and peak-to-peak jitters at operating bandwidth are 1.05 to 1.71 ps and 8.4 to 12 ps, respectively.

Low-Power Built-in Jitter Injection Using Linearized Phase Interpolator

Low-power circuits built in optical transceivers that can be used in characterizing phase interpolators (PIs) and injecting jitter to test the tolerance of clock-data recovery (CDR) are presented. The novelty is in digitally controlling a precompensated PI in the feedback path of a phase lock loop. The latter is driving the sampling clock of the digital-to-analog converter at the transmitter. To improve the accuracy of jitter mask measurements at the receiver, the nonlinearity of used PI is compensated by the mean of a programmable lookup table (LUT), which is populated using a built-in test circuitry. As well, the LUT can serve to allow for generating jitter frequencies that are out of phase-locked loop bandwidth. Both linearization and jitter injection methods are generic and can be applied to any wireline transceivers at both client and modem interface sides.

Phase field model derivation for rapid crystal growth in polycrystalline alloys

A phase field model of rapid multi–grain growth is developed. Using a multi–phase model for polycrystalline growth in multi–component alloying systems and the model of fast phase transformations, the Gibbs free energy change on crystallization is formulated as a driving force for polycrystalline growth. The model of fast phase transitions, which introduces not only classical slow variables (concentration, chemical potential and phase field), but also the fast ones (diffusion flux and gradient flow), was used to capture short periods of times usually occurring in the rapid solidification and in the fast solid-state transformations. The evolution equations for the fast crystallization are written using multi–phase interpolation functions among growing polycrystallites.

Fast Side Information Generation for High-Resolution Videos in Distributed Video Coding Applications

Distributed video coding (DVC) is an attractive and promising scheme that suits the constrained video applications, such as wireless sensor networks or wireless surveillance systems. In DVC, estimation of fast and consistent side information (Տį) is a critical issue for instant and real-time decoding. This issue becomes even more serious for high-resolution videos. Therefore, to minimise the side information estimation computational complexity, in this work, a computationally low complex DVC codec is proposed, which uses a simple phase interpolation (Phase-I) algorithm. It performs faster for all resolutions videos, and significant results are achieved for high-resolution videos with a large group of pictures (GOP). For the proposed technique, the computation time rapidly decreases with an increase in resolution. It performs 221% to 280% faster from conventional frame interpolation method for high-resolution videos and large GOP at the cost of little degradation in the visual quality of estimated side information.

Pre-calibration of the phase interpolator of a precision time interval meter

The problems of precision measurements of time intervals are considered, the results of which are necessary, for example, to assess the metrological characteristics of the structural complexes of space navigation systems. A precision time interval meter has been designed. The relationship between the meter readings and the size of the measured value is established. A technique for preliminary calibration of a phase interpolator with an uneven quantization step from the composition of a precision time interval meter was developed and tested. The optimal value of the reference frequency was selected and the optimal size of the measuring matrix, consisting of logic gates connected in series, was calculated. The degree of influence of the crystal temperature of the FPGA integrated circuit on the operation of the phase interpolator is determined. The requirements for test signals were developed and the possibility of using the reference signals of the secondary standards of time and frequency (for example, the State secondary standard of units of time and frequency VET 1-7) during the preliminary calibration of the phase interpolator was evaluated. Special software has been developed for determining the boundaries of the sub-quanta of the phase interpolator with a resolution of one picosecond, and the probability density functions of the transition process from one subquantum to the next are calculated. The requirements for the spectral composition of the frequency of the reference signal are given and the frequency detuning of the test signal relative to the reference is determined. Verification of the developed methodology for preliminary calibration of the temporal position of the phase transitions of the interpolator was carried out by repeated calibrations and comparison of the results.

A Fast Settling Fractional-$N$ DPLL With Loop-Order Switching

The enhancement in the settling response of frequency synthesizers would open up prospects for new applications such as spread spectra and frequency hopping systems. Toward deriving a methodology for a fast settling response, we present a switched-loop digital phase locked loop (DPLL) incorporating an integral-derivative controller-based subsystem. The dominant features accelerating the settling response with low jitters in this DPLL are: 1) hybrid phase detection with a state machine using differential and double integration filtering effect and 2) a time-interleaved direct digital synthesizer (DDS)-based digital-to-time converter (DTC) with stable-edge sampling. A 5-GHz fractional- $N$ DPLL (FNDPLL) has been implemented in CMOS 65-nm-LL technology with the proposed technique of loop-order switching. The measured results of the implemented FNDPLL highlight that the system is capable of fastest reported frequency settling to ±25-ppm error within 1.5 ${\mu }\text{s}$ , using a reference clock frequency of 100 MHz. With one-time calibration, the downsampled output of DDS array-based phase interpolator achieves an integral nonlinearity (INL) of 0.25 ps, as a fractional divider in the loop.

An improved phase interpolation estimator

The capability of time‐shifting‐based phase difference method against noise can be considerably improved with the increase of the translation coefficient. However, the anti‐noise performance of the traditional method is limited due to the wrapped phase problem. In order to obtain high accuracy of estimate, this paper proposes an improved phase interpolation estimator which is derived in terms of the time‐shifting‐based phase difference method. First, the estimator utilizes three segments of signal in the time domain to build two sets of frequency estimate. Then the absolute difference of the frequency estimate between the two sets can be calculated. Subsequently, four frequency estimates with minimal absolute difference are selected. Finally, the one in four frequencies owning maximum energy is selected as the final frequency estimate. Simulation results show that the improved algorithm can overcome the wrapped phase problem to some extent and can achieve better noise immunity than traditional algorithms. © 2019 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-[Formula: see text][Formula: see text]m CMOS technology with supply voltage of 1.8[Formula: see text]V. The output clocks with cycle-to-cycle jitter of 2.13[Formula: see text]ps at 1.6[Formula: see text]GHz. The phase noise of VCO is [Formula: see text]137[Formula: see text]dBc/Hz at an offset of 100[Formula: see text]MHz and total power consumed by the proposed PLL is 2.63[Formula: see text]mW at 1.6[Formula: see text]GHz.

A CDR System Based on Improved Second Order Digital Filter, Hysteretic Voter and Phase Interpolator

The proposed Clock and data recovery system (CDRS) has three improved parts. The second order digital filter with rounding algorithm implements fractional gain and avoids direct current quantization noise which varies between -q/2 and +q/2 while that of traditional filter varies between 0 and +q (q is quantization step). The hysteresis majority voter can combat high frequency and strong jitter especially in quasi-steady state. The improved Phase interpolator (PI) has much smaller current-switching glitch and phase glitch since the weighting current changes gradually instead of steeply. The optimized CDRS can handle up to ±6000ppm (parts per million) frequency offset and the phase resolution is 1.4º/LSB (Least significant bit) according to analysis. The simulations of jitter transfer function and jitter tolerance by Matlab, simulations of phase noise by spectre using Verilog+VeriloA model, and measurements of frequency offset and jitter tolerance all show its good performance.

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation

Skews between data and strobe signals can occur in HBM transceivers due to process and voltage variations across the base die. Skew compensation is introduced into the deserializers of our quarter-rate single-ended receiver for next-generation unmatched source-synchronous HBM interfaces. Data and strobe signals are energy-efficiently realigned by using a 45° strobe phase DQS45. This phase, which is equidistant between quadrature strobe phases DQS0 and DQS90, is generated by a digital type phase interpolator of our receiver. The transceiver, including the proposed receiver, was designed and fabricated in a 65nm CMOS process. The receiver corrects skews to within 7.8ps at a data-rate of 6.4Gb/s, with an energy cost of 0.83pJ/bit per pin.

A 2.2-GHz 3.2-mW DTC-Free Sampling $\Delta\Sigma$ Fractional-$N$ PLL With −110-dBc/Hz In-Band Phase Noise and −246-dB FoM and −83-dBc Reference Spur

This paper presents the first sampling $\Delta \Sigma $ fractional- $N$ phase-locked loop (PLL) without a digital-to-time converter (DTC), whose design is challenging and requires complex calibration. A linear slope generator (LSG) is employed to generate a linear waveform, which has a large linear phase-to-voltage conversion range. Instead of modulating the reference signal by the DTC, phase dithering is performed at the feedback path through the combination of the LSG and a multi-modulus divider (MMDIV) with multi-phase generation. The reference signal then directly samples the linear LSG output waveform to output a sampled voltage corresponding linearly to the resulting phase error. All these enable the sampling phase detector to handle large phase dither step provided by a phase interpolator (PI), thus eliminating the need for the DTC and the associated calibration. This 2.2-GHz PLL achieves −246-dB FoM with an in-band phase noise of −110 dBc/Hz and −82-dBc reference spur while consuming only 3.2 mW in a 130-nm CMOS process.

Computationally Efficient Phase Shift Plus Interpolation Seismic Migration Method

In this letter, we propose a computationally efficient implementation of the phase shift plus interpolation (PSPI) seismic migration technique. The PSPI is among the well-known migration techniques in the frequency-wavenumber ( $\omega -k_{x}$ ) domain that accounts for lateral velocity variations in the earth subsurface. However, the large number of complex multiplications required to perform PSPI makes this method computationally expensive. The proposed method replaces the use of complex multiplications in the frequency-wavenumber ( $\omega -k_{x}$ ) domain with real additions, reducing the computational complexity greatly. It also replaces the real-by-complex multiplications with real multiplications. It does so by using the fact that the PSPI technique maintains the amplitude and shifts the phase of seismic wavefields in the passband region of the extrapolators while attenuating the amplitude and maintaining the phase of the wavefield in the evanescent region of the extrapolators. The proposed method was tested by performing 2-D poststack depth migration to the well-known SEG/EAGE Salt Model. The computational complexity in the $\omega -k_{x}$ domain was reduced by 76.9%, while producing an accurate migrated section of the salt model.

A Low-Pass Filter Bandwidth Adaptation Technique for Phase Interpolators

This paper presents a technique to automatically adapt the bandwidth of the low-pass filter (LPF) of the phase interpolator (PI) used in bang-bang clock and data recovery (CDR) circuits. A technique for introducing the reference nonlinearity in the presence of PI’s nonlinearity is presented. This reference is used for LPF bandwidth adaptation. A mathematical model for the PI nonlinearity and introduction of reference nonlinearity is proposed. Using this model, analysis and design of the proposed bandwidth adaptation are done. The technique is verified by simulations and Si-measurements using a full-rate bang-bang CDR, which is fabricated in 180-nm CMOS technology. The PI occupies an area of 0.014 mm2 and consumes 1.1 mA for 1-GHz PI clock frequency while working on 1.8-V supply.

Phase‐interpolator‐based glitch‐free fractional frequency divider with track‐and‐hold technique

This Letter presents an 8-bit fractional frequency divider by utilising current-mode phase interpolator (PI) for digital phase-locked loops. A novel track-and-hold circuitry is proposed between the PI and divide-by-2. It can remove the glitches generated by the current-interpolation structure. This method also relaxes the requirement of the minimum input frequency, while maintaining the same output frequency. The proposed fractional frequency divider is designed and fabricated with a 65-nm CMOS technology. It dissipates a DC power of 0.8 mW from a 1.2 V supply. The measurement result shows that the fractional frequency divider achieves an uncalibrated in-band spur of -43 dBc.

Analysis of Timing Accuracy and Sensitivity in a RF Correlation-Based Impulse Radio Receiver With Phase Interpolation for Data Synchronization

This paper presents an analytical method for the performance evaluation of the correlation-based impulse radio (IR) receivers, which detect the data based on synchronizing the received signal with a locally generated template pulse. In this paper, a phase interpolation technique is employed to preserve synchronization accuracy with low power consumption. The analytical method computes the spectral density of jitter at the phase interpolator output, resulting from both flicker and thermal noise components. The analysis considers the aliasing phenomenon due to the sampling of the noise to predict the induced jitter accurately. Bit error rate (BER) of the receiver is also statistically estimated in terms of the induced jitter on the template pulse, the noise effect of the receiver chain, and the template signal level. The proposed estimation procedure is validated by comparing its results with transient noise simulations. It is shown that increasing the template signal range in the correlator and improving the linearity of the phase interpolation transfer curve, at a given power consumption, enhances the receiver sensitivity by 2 and 3.5 dB, respectively. The BER estimation results also reveal that the effect of the template signal jitter on the sensitivity of the correlation-based IR receivers becomes dominant with the increasing input signal level.

A High-Precision 2.5-ps RMS Time Synchronization for Multiple High-Speed Transceivers in FPGA

The high-speed serial transceiver plays a key role in the high-speed data transmission. Because of the independent clock network in each transceiver, there exist random skews between the multiple transceivers each time the system reinitializes. In the system of data transmission, these random skews are always permitted and the intrachannel synchronization is guaranteed by inserting some same comma codes in each channel. However, for the strict clock distribution system, these random skews are unacceptable. To address this problem, a scheme combined of a tunable phase interpolator (PI) and a high-precision time-to-digital converter (TDC) is presented. A plain TDC is employed to measure the skews of parallel clocks in multichannels with bin size of ~10.2 ps and precision of ~18.0 ps. The method of multiple measurements average is adopted to further improve the TDCs performance. On this basis, time synchronization with root mean square (rms) of ~2.5 ps and peak-to-peak value of ~14.7 ps is implemented in a 20-nm fabrication process ultrascale field programmable gate array (FPGA). Compared to the measured results (rms of ~22 ps and peak-to-peak value of ~105 ps) of the Xilinx self-phase alignment method, the presented scheme has more than six times performance improvement. In addition, this scheme can lock the delay between different channels to arbitrary configurable offsets, making it very suitable for scenarios where multichannel latencies are strictly restricted.

A 5–10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package

This paper presents an energy-efficient I/O interface with a 3-D flip chip package. The I/O interface is composed of a transmitter and a receiver. The transmitter consists of a pseudo-random bit sequence generator and an output buffer. The receiver employs a full-rate forwarded-clock structure that is composed of a novel current-domain equalizing sampler with a 10 Gb/s sampling rate for data recovery and a low-power clock recovery circuit with dual-injection-locked oscillators. The proposed sampler utilizes a current sampling structure and merges a shunt-peaked amplifier with 20-GHz bandwidth for data recovery. Meanwhile, clock recovery implements a phase interpolator achieving phase deskew larger than one data unit interval. A 3-D flip chip package with silicon substrate is utilized for multiple I/O channels integration. The chip was fabricated in a 65-nm CMOS process in an area of 0.42 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measurement results show that the I/O interface can realize a 5-10-Gb/s data rate with bit error rate less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> across 5-mm redistribution layers in a silicon substrate whose loss is 3~4 dB at Nyquist bandwidth.