Phase Interpolation Research Articles

A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications

A Digital-to-Time Converter based (DTC-based) fractional-N digital phase-locked loop (DPLL) using probability-density-shaping (PDS) spur immunity and quantization phase (Q-noise) reduction techniques is presented. PDS-DSM is used to generate a loop spur immunity control code for DTC. A diff type dither is proposed to further suppress the fractional spur. The loop nonlinearity will not cause fractional spurs if certain conditions are obeyed. Moreover, to reduce the quantization noise, a configurable Phase Interpolator (PI) with 0.125/0.25/0.5/1.0 division step is integrated with a multi-module divider (MMDIV), leading to an 18-dB Q-noise suppression. A reference doubler with duty-cycle correction is adopted to further reduce phase noise. The fractional spurs are greatly mitigated by combining the PDS-DSM and phase interpolator. A DPLL prototype using the aforementioned techniques was designed in a 40-nm standard CMOS process, occupying a 0.99 mm2 silicon area. At a near-integer-N frequency, i.e., near 2.23 GHz, with PDS turned on and off, the post-layout simulated fractional spur is −59 dBc and −20 dBc, respectively. The RMS jitter of the whole chip is 4.218 ps, corresponding to a figure of merit (FOM) of −220.5 dB.

A 1.9-ps 8× phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration

This paper presents a 1.9-ps 8× phase interpolation time-to-digital converter (PI-TDC). This architecture enhances the resolution and conversion speed in cooperation with phase interpolation, high-frequency readout, and reset techniques. The prototype PI-TDC is designed in a 65-nm CMOS process with a 1-V power supply, achieving a 1.9-ps resolution at 2.5-GS/s. The simulated DNL is 0.85-LSB, and INL is 0.64-LSB. This PI-TDC is applied to a high-speed time-based analog-to-digital converter (TB-ADC) with a high-performance voltage-to-time converter (VTC) and the capacitance compensation self-calibration (CCS-CAL). The high-speed TB-ADC achieves 8-bit at 1.6-GS/s with PVT robustness while exhibiting a Walden FoM of 52.1-fJ/conv.-step.

A Calibration-Free Digital-to-Time Converter for Phase Interpolation-Based Fractional-N PLLs

In this paper, a fractional frequency division phase-locked loop based on phase interpolation is proposed and implemented using the TSMC 0.11 μm CMOS process. Compared with the conventional phase-locked loop, a digital time converter (DTC) module is added to this phase-locked loop, and the DTC module can reduce the fractional spurious by phase interpolation. The circuit and analysis method of this DTC module are given in this paper. Unlike the existing approaches, the proposed DTC is calibration-free, and the error introduced by it is only related to the DAC adopted in the DTC. In addition, the accuracy of the DTC is 8 bits. Finally, this paper verifies the proposed quantization noise reduction technique using a 0.11 μm CMOS process. The proposed FNPLL achieves the overall power consumption of 20.3 mW, the noise of −117dBc/Hz@1 MHz and −138dBc/Hz@10 MHz, and the RMS jitter of 0.860ps. The area of the proposed FDIV is 60×245μm2, and the power consumption is 1.356mW. The phase noise of the proposed FNPLL in the fractional division mode is just 2dB higher than that in the integer division mode.

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

SummaryThis paper reports a bang‐bang clock and data recovery circuit (BBCDR) with an ultra‐wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6‐to‐38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate‐current‐mismatch technique. Moreover, we accurately obtain an eight‐phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter‐based phase interpolator. A 65‐nm prototype of the developed BBCDR occupies an area of 0.07 mm2 and attains a bit error rate of less than 10−12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32‐Gb/s non‐return‐zero input, thus leading to 0.769‐pJ/bit energy efficiency.

The Design of a Phase Interpolator [The Analog Mind

The Design of a Phase Interpolator [The Analog Mind

A 50-ps Gated VCRO-Based TDC With Compact Phase Interpolators for Flash LiDAR

This article describes a small footprint, low power gated voltage-controlled ring oscillator (VCRO)-based Time-To-Digital converter (TDC) for Flash Light Detection and Ranging (LiDAR) applications. A group of compact local phase interpolators (PIs) are used to improve the resolution, which is highly area-saving and compatible with in-pixel TDC structure. A non-reset operation mode is introduced to increase the linearity by taking advantage of the dynamic element matching (DEM) property. The proposed TDC has been fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> HV-CMOS technology in a 32 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times32$ </tex-math></inline-formula> array, achieving a resolution of 50 ps. A Phase Lock Loop (PLL) is adopted to track the process, voltage, and temperature (PVT) variations and make the resolution tunable. A power-saving analog buffer is used to distribute the stable control voltage to all the in-pixel TDCs. Measurements show a good linearity performance and array uniformity (a deviation of only 0.89 ps), making it suitable for Flash LiDAR applications.

A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications

A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recovery (CR) loop with an adaptive decimation filter (ADF) function to remove the jitter and phase noise of the input clock, and generate a phase-aligned clean output clock. In addition, by adopting an all-digital multi-phase multiplying delay-locked loop (MDLL), eight low-jitter evenly spaced reference clocks that are required for the PI are generated. In the proposed DJA, both the MDLL and PI-based CR are first-order systems, and so this DJA has the advantage of high system stability. In addition, the proposed DJA has the benefit of a wide operating frequency range, unlike general PLL-based jitter attenuators that have a narrow frequency range and a jitter peaking problem. Implemented in a 40 nm 0.9 V CMOS process, the proposed DJA generates cleaned programmable output clock frequencies from 2.4 to 4.7 GHz. Furthermore, it achieves a peak-to-peak and RMS jitter attenuation of –25.6 dB and –32.6 dB, respectively, at 2.4 GHz. In addition, it occupies an active area of only 0.0257 mm2 and consumes a power of 7.41 mW at 2.4 GHz.

Deep learning assisted time-varying channel estimation in multi-user mmWave hybrid MIMO systems

Hybrid analog/digital multiple input multiple output (MIMO) system is proposed to mitigate the challenges of millimeter wave (mmWave) communication. This architecture enables utilizing the large array gain with reasonable power consumption. However, new methods are required for the channel estimation problem of hybrid architecture-based systems due to the fewer number of radio frequency (RF) chains than antenna elements. Leveraging the sparse nature of the mmWave channels, compressed sensing (CS)-based channel estimation methods are proposed. Recently, machine learning (ML)-aided methods have been investigated to improve the channel estimation performance. Additionally, the Doppler effect should be considered for the high mobility scenarios, and we deal with the time-varying channel model. Therefore, in this article, we consider the scenario of time-varying channels for a multi-user mmWave hybrid MIMO system. By proposing a Deep Neural Network (DNN) and defining the inputs and outputs, we introduce a novel algorithm called Deep Learning Assisted Angle Estimation (DLA-AE) for improving the estimation of the Angles of Departure/Arrival (AoDs/AoAs) of the channel paths. In addition, we suggest Linear Phase Interpolation (LPI) to acquire the path gains for the data transmission instants. Simulation results show that utilizing the proposed DLA-AE and LPI methods enhance the time-varying channel estimation accuracy with low computational complexity.

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS

This paper presents a low-power, high-bandwidth wireline transceiver for chiplet. The transceiver uses a new technology of correlated non-return to zero (CNRZ) to improve the pin efficiency and reduce the noise of the common mode and crosstalk (CMN and XTALK). The transmitter adopts a 4:1 multiplexer (MUX) and a special voltage-mode driver [source series terminated (SST)] to improve the power efficiency. The receiver utilizes a low jitter clock-and-data alignment (CDA) based on high resolution phase interpolator (PI) and a MINI-PLL with differential filter based to improve the jitter performance of the receiver’s clock. In addition, a special continuous-time linear equalizer (CTLE) is introduced into the multiple-input compare (MIC) based decode circuit to reduce the receiver’s bit error rate (BER). This transceiver is designed with a 28 nm CMOS process technology and supplied with 0.9/1.2 V. Simulation results show that this transceiver can operate at 200 Gb/s with the 33.3 Gb/s single-wire data rate and a power consumption of 1.06 pJ/b. The transceiver’s BER is less than 1E-15 and eye-wide-opening is 12.02 ps (48.08% UI), which is under 10 dB channel loss at 20 GHz Nyquist frequency.

A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications

This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC’s resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply.

Orthogonal phase mixing for improved linearity phase interpolator

As the demand for high-speed low-power transceivers grows, it is critical to have precise clock timing circuits such as phase interpolators (PI) that allow maximizing link margin. A linearization technique which optimizes linearity without increasing power and area is presented. Implemented in a 7-nm complimentary metal oxide silicon (CMOS) technology, PI achieves less than 0.5 integral non-linearity (INL) while consuming only 184 μA from a 0.75-V supply at 4.3 GHz.

A Multichannel, High-Bandwidth Wirelane Receiver for D2D Interconnects

This paper proposes a multichannel and high-bandwidth (BW) receiver for standard packaging die-to-die (D2D) interconnects. The receiver adopts forward clock (FCK) architecture of the high-density transmission standard, which consists of 16 high-speed data paths and a pair of low-speed differential clocks for 512 Gbps BW. To reduce the chip area and power consumption, a common minimal phase-locked loop (MINI-PLL) and data adjustment (CDA) circuit to replaces the clock data recovery circuit (CDR) in the traditional receiver. A delay-matching circuit is adopted to combat PVT variation and lane skew. In addition, a high linearity phase interpolator (PI) circuit design is used in the minimum phase-locked loop (MINI-PLL) to adjust the clock phase and improve the clock jitter performance. Using 28 nm CMOS technology, the overall link power consumption is 1.56 pJ/b. Bit error rate (BER) is less than 10−15 under the real S-parameters with a channel loss of 10db@16GHz.

Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL

We present a high-accuracy, low-jitter, multi-phase clock generator (MPCG) based on a multi-phase, injection-locked ring oscillator (MPIL-ROSC) with a quadrature delay-locked loop (QDLL). The QDLL tunes the ring oscillator (ROSC) self-oscillation frequency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{{0}}$ </tex-math></inline-formula> ) and provides it with multi-phase injection signals. The proposed architecture breaks the intrinsic tradeoff between jitter and phase accuracy in two-phase injection-locked ROSCs. The MPCG’s eight-phase output clock drives a 7-bit phase interpolator (PI) for phase and frequency deskew. A 1.2-V 65-nm CMOS MPCG prototype chip has a better-than-1° eight-phase accuracy and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$58.8~\mathrm {fs}_{\mathrm {rms}}$ </tex-math></inline-formula> jitter (integrated from 100 kHz to 1 GHz), while consuming 15.6 mW at 7 GHz, yielding a −252.7-dB figure of merit ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {FOM}_{\mathrm {jitter}}$ </tex-math></inline-formula> ). The peak-to-peak integral nonlinearity (INL) and the peak-to-peak differential nonlinearity (DNL) of the PI are less than 1.9 and 1.2 LSB, respectively, across a frequency range from 5 to 8 GHz.

A delay cell with duty-cycle correction and parasitic compensation for large array indirect time-of-flight CMOS image sensors

Large array indirect time-of-flight (ToF) CMOS image sensors use a self-compensating voltage-controlled delay line (VCDL) to decrease the peak current of the demodulation circuit. However, the ToF detection error is affected by the output duty cycle of the self-compensation VCDL. This paper analyzes the relationship between the output duty cycle of the self-compensation VCDL and the ToF detection error. A delay cell with duty cycle correction and parasitic compensation is proposed. A phase interpolator is also used to improve the output phase resolution of the self-compensating VCDL. This design is implemented using the 0.11μm CMOS process. The post-simulation results show that the correction range of this design is 0.9% to 98% at 100 MHz. By applying the proposed delay cell to the self-compensating VCDL, the delay of one delay cell is reduced by 163 ps due to the parasitic compensation circuit. Moreover, the ToF detection error decreases by 2.03 cm compared to the traditional structure.

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET

This article describes the design of a 1.24-pJ/b 112-Gb/s PAM4 transceiver test chip in 7-nm FinFET for in-package die-to-die communication. The receiver supports 0–1.2-V input common mode and utilizes a single-stage active inductor-based CMOS continuous-time linear equalizer (CTLE) with 12 data slicers and two error slicers. The quad-rate voltage-mode transmitter implements delay-based sub-UI two-tap FFE and digital I/Q and DCC clock calibration. A single-phase clock from a wideband <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> phase-locked loop (PLL) is distributed to eight transceiver channels. In each channel, an injection-locked oscillator (ILO) generates eight-phase clocks that feed an 8-bit CMOS phase interpolator (PI). The transceiver achieves < 1e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> bit error rate (BER) over 30-mm channel at 106.25 Gb/s and over 20-mm channel at 112 Gb/s.

A 2.4–8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input–Output Phase Detection

This paper presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic random-access memory interface in 28-nm CMOS technology. A direct input-output comparison using a sub-sampling technique reduces the effect of a timing mismatch of a replica delay line for synchronizing an input clock and output strobe clock. A divided clock samples the input clock for phase alignment. A 4-b analog-to-digital converter was used for input phase acquisition. The output phase is aligned with respect to the sampling clock phase using a bang-bang phase detector. Two DLLs for the input-output synchronization are implemented in a cascade structure, and the loop delay of the replica delay line is considerably reduced. In the proposed DLL, a PR delay line using an 8-phase clock generator is adopted for linearity to reduce the phase difference of the phase interpolation from π/2 to π/4. The resolution of the PR-DLL is 7-b of 2π, which consists of a 3-b coarse and a 4-b fine control. The DLL operates from 2.4 to 8 GHz, and the power dissipation at the maximum input frequency is 20.2 mW. The measured clock root mean square jitter was 1.68 ps. According to the simulation results, the phase mismatch between the input and output clocks was reduced by 80.5%.

A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR

This article presents a 50-Gb/s optical transmitter (TX), consisting of a 40-nm distributed CMOS driver and a 180-nm silicon-photonic modulator. A lumped-segment Mach–Zehnder modulator (LS-MZM) is developed for high bandwidth (BW) four-level pulse amplitude (PAM-4) modulation. A multi-segment driver with limiting outputs is co-designed, which is distributed into each LS-MZM segment. By grouping these LS-MSM segments in a thermometer code, high-linearity modulation is realized without the need of power-hungry high-swing linear drivers. To improve the optical PAM-4 signal integrity, in-segment multiplexing along with clock phase interpolation is adopted to synchronize the electrical and optical signals across all segments. The hybrid coupling between the driver and modulator is devised to boost the BW of the high-speed data path, while a half-rate clock and data recovery (CDR) circuit is integrated to remove the accumulated jitter. Measurements show that the TX exhibits an extinction ratio (ER) of up to 9.8 dB and a 0.99 ratio of the level mismatch. A figure-of-merit (FoM) of 1.39 pJ/bit/dB corresponds to a 682-mW power, which can be further reduced by 40%, at the cost of a degraded ER of 4 dB. The PAM-4 CDR helps to achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 10^{-12}$ </tex-math></inline-formula> BER and >0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{U}I_{\mathrm {pp}}$ </tex-math></inline-formula> jitter tolerance (JTOL) from 10 to 100 MHz.

GPU accelerated Cartesian GRAPPA reconstruction using CUDA

Background and ObjectiveGRAPPA (Generalized Auto-calibrating Partially Parallel Acquisition) is an advanced parallel MRI reconstruction method (pMRI) that enables under-sampled data acquisition with multiple receiver coils to reduce the MRI scan time and reconstructs artifact free image from the acquired under-sampled data. However, the reduction in MRI scan time comes at the expense of long reconstruction time. It is because the GRAPPA reconstruction time shows exponential growth with increasing number of receiver coils. Consequently, the conventional CPU platforms may not adhere to the requirements of fast data processing for MR image reconstruction. MethodsGraphics Processing Units (GPUs) have recently emerged as a viable commodity hardware to reduce the reconstruction time of pMRI methods. This paper presents a novel GPU based implementation of GRAPPA using custom built CUDA kernels, to meet the rising demands of fast MRI processing. The proposed framework exploits intrinsic parallelism in the calibration and synthesis phases of GRAPPA reconstruction process, aiming to achieve high speed MR image reconstruction for various GRAPPA configuration settings using different number of receiver coils, auto-calibration signals (ACS), sizes of GRAPPA kernel and acceleration factors. In-vivo experiments (using 8, 12 and 30 receiver coils) are performed to compare the performance of the proposed GPU accelerated GRAPPA with the CPU based GRAPPA extensions and GPU counterpart. ResultsThe results indicate that the proposed method achieves up to ≈47.8× , ≈17× and ≈3.8× speed up gains over multicore CPU (single thread), multicore CPU (8 thread) and Gadgetron (GPU based GRAPPA) respectively, without compromising the reconstruction accuracy. ConclusionsThe proposed method reduces the GRAPPA reconstruction time by employing the calibration phase (GRAPPA weights estimation) and synthesis phase (interpolation) on GPU. Our study shows that the proposed GPU based parallel framework for GRAPPA reconstruction provides a solution for high-speed image reconstruction while maintaining the quality of the reconstructed images.

A high precision phase measurement system implemented in FPGA with phase interpolator.

High precision timing distribution is crucial to many large scale cosmology and particle physics experiments. Besides the space and energy information, the accurate timing provides an extra dimension for physics event reconstruction. In the timing distribution system, accurate clock phase measurement is an indispensable tool to monitor the phase drift and to achieve accurate phase adjustment. This paper introduces a novel phase measurement method implemented in the Xilinx Field Programmable Gate Array (FPGA). It uses the dedicated phase interpolator in the multi-gigabit transceiver. A design based on this method is implemented within the Kintex Ultrascale series FPGA. The preliminary test result shows that a sub-picosecond level precision is achieved. With this system, the nonlinearity of the phase adjustment in the Xilinx transceiver is measured.

An Innovative Way of Using Coherently Radiating Periodic Structures for Phased Arrays With Reduced Number of Phase Shifters

This article presents an innovative design technique for feeding phase antenna arrays using coherently radiating periodic structure (CORPS) technology for reducing the number of phase shifters (PSs) in limited-scan applications with low sidelobe level (SLL). The proposed configuration is implemented taking advantage of the phase interpolation property of a CORPS network of one layer. This configuration is built by interconnecting <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 3$ </tex-math></inline-formula> CORPS networks in a strategic way in order to provide a reduction in the number of PSs while maintaining the scanning capability. Experimental results and full-wave simulations based on CST Microwave Studio reveal that the proposed design technique reduces the recombination losses and generates a better phase slope with respect to the basic CORPS network providing a reduction in the number of PSs. As a novel contribution, this article provides the full antenna system design in order to analyze and study the PSs reduction performance and scanning capabilities of the proposed technique to feed linear antenna arrays. The proposed design technique provides a reduction in the number of PSs for a scanning range of ±25° in linear arrays. The array design model includes the application of the raised cosine amplitude distribution to generate a radiation pattern with minimum SLL. The linear array system was validated by experimental measurements of the full system prototype and full-wave simulations results are provided to verify the accuracy of the array model and to take mutual coupling into account. The proposed case provides a good design compromise with respect to other cases in the state of the art.