Low-Power Built-in Jitter Injection Using Linearized Phase Interpolator

Abstract

Low-power circuits built in optical transceivers that can be used in characterizing phase interpolators (PIs) and injecting jitter to test the tolerance of clock-data recovery (CDR) are presented. The novelty is in digitally controlling a precompensated PI in the feedback path of a phase lock loop. The latter is driving the sampling clock of the digital-to-analog converter at the transmitter. To improve the accuracy of jitter mask measurements at the receiver, the nonlinearity of used PI is compensated by the mean of a programmable lookup table (LUT), which is populated using a built-in test circuitry. As well, the LUT can serve to allow for generating jitter frequencies that are out of phase-locked loop bandwidth. Both linearization and jitter injection methods are generic and can be applied to any wireline transceivers at both client and modem interface sides.