Design of High-speed Serial data Generation Module with Controllable Edge Jitter Based on Phase Interpolation

Abstract

At present, high-speed serial transmission technology is gradually replacing parallel transmission as the mainstream. Due to the influence of power supply noise, inter symbol crosstalk and transmission channel, various jitters will occur in the process of data transmission, which will have a significant impact on the whole system. It is more and more important to improve the jitter tolerance and clock data recovery ability of the receiver of high-speed serial communication system. In order to effectively test the jitter tolerance and clock data recovery of high-speed serial communication system, the serial signal source needs to have the function of controllable jitter injection. After comparing various jitter injection methods, a jitter injection method using phase interpolation to change the edge position of code pattern is introduced in this paper. Through the dynamic reconfiguration function of FPGA, the phase of serders output sampling clock edge is dynamically and periodically changed to realize the jitter control of output data edge, so as to realize the jitter injection of high-speed data. Through this method, the jitter injection of sine wave and square wave with amplitude of 0 ∼ 2ui and frequency of 0 ∼ 12.5mhz is verified on 0.5 ∼ 32gbps serial signal. It can provide controllable jitter signal for testing jitter tolerance and clock data recovery ability of high-speed serial communication system.