Design of High Speed Serial Data Generation Module with Controllable Output Edge Jitter Based on Delay Line

Abstract

In the high-speed serial communication system, due to the influence of power supply noise, inter symbol crosstalk and transmission channel, various jitters will occur in the process of data transmission, which will have a significant impact on the whole system. It is more and more important to improve the jitter tolerance and clock data recovery ability of the receiver of the high-speed serial communication system. In order to effectively test the jitter tolerance and clock data recovery of high-speed serial communication system, the serial signal source needs to have the function of controllable jitter injection. After comparing various jitter injection methods, this paper proposes a method to adjust the clock edge position on the reference clock of high-speed serial interface to realize jitter control. This method generates different jitter based on the change of the output delay of the internal delay line of FPGA periodically. The jitter is injected into the serders reference clock and transmitted to the high-speed serial data through the phase-locked loop to realize the jitter injection of the output data. This method can realize jitter injection with jitter frequency of 1MHz and resolution of 3ps, which provides an effective test signal for testing jitter tolerance and clock data recovery ability of high-speed serial communication system.