Phase Interpolation Research Articles

Full-field three-dimensional system calibration for composite surfaces reconstruction

The accurate calibration of composite surface measurement systems for specular and diffused surface is of great importance in a number of industrial applications. This paper addresses the challenges in calibrating composite surface reconstruction by proposing a comprehensive full-field calibration method. The principal innovation is the construction of a comprehensive reference phase and the pixel-by-pixel calibration of system parameters within the same coordinate system. The details are as follows: (1) construct a complete reference phase for the composite surfaces through external parameter constraints phase fusion and interpolation; (2) calibrate the mapping relationship coefficients, compensate the accuracy degradation of the partial reflection. Experimental results validate the accuracy of the full-field calibration data, demonstrating the effectiveness and feasibility.

Computational vibration mitigation using phase interpolation in digital holographic microscopy for overlay metrology

Digital holographic microscopy retrieves amplitude and phase information of an image which allows us to computationally correct for imperfections in the imaging optics. However, digital holographic microscopy is an interferometric technique that is inherently sensitive to undesired phase variations between object and reference beam. These phase variations lower the fringe contrast if they are integrated over a finite exposure time which leads to a reduced amplitude of the retrieved image. This results in significant errors in applications that rely on a stable and accurate amplitude measurement, such as optical overlay metrology in the semiconductor industry. We present experimental results on a computational vibration mitigation method for the application of overlay metrology using phase interpolation between a sequence of measured holograms and demonstrate its capability to improve metrology precision in an overlay metrology application that uses digital holographic microscopy.

A clock synchronization and trigger distribution scheme for China Spallation Neutron Source

China Spallation Neutron Source (CSNS) is a complex system engineering composed of particle accelerators, a target station, and neutron spectrometers with various equipment types and distribution. The collaborative operation of the equipment requires accurate clock synchronization and trigger distribution. Currently, to meet the requirements of different system devices, clock synchronization and trigger distribution in CSNS are implemented based on different methods, resulting in complex clock and trigger networks, demanding upgrades, and a lack of unified timestamps. This paper proposes a clock synchronization and trigger distribution scheme based on the field-programmable gate array (FPGA) and single-mode dual-core fiber link. The decoupling of clock phase synchronization and time base synchronization improves the frequency of phase compensation. Benefiting from the phase interpolator (PI) in the FPGA transceivers, high-precision phase compensation and phase deterministic control are realized, achieving picoseconds synchronization precision and stability in the four-level network. Based on the custom lightweight link layer protocol, by optimizing the routing method of data frames and adopting priority control, the transmission of multiple data is realized, and the hardware delay of the critical data, such as interlock, is guaranteed to be less than 1.5 μs in the four-level system. The scheme provides a general precise clock synchronization and distributed trigger method for CSNS devices, simplifies the system complexity, and is conducive to the system upgrade in the second stage.

A 16 Gb/s serial link transceiver with active inductor based CTLE and 3-tap DFE in 12-nm FinFET CMOS

This paper presents a 16 Gb/s serial link transceiver implemented in 12-nm FinFET CMOS technology. The equalization scheme incorporates a 3-tap feed-forward equalizer (FFE) in the transmitter, a 5-stage continuous time linear equalizer (CTLE), and a 3-tap decision-feedback equalizer (DFE) in the receiver. The proposed FFE structure offers small step size and flexible configuration. The CTLE's high-frequency boost is augmented by integrating an active inductor. A high-accuracy clock and data recovery (CDR) circuit, featuring a cascaded two-step analog phase interpolator (PI) structure, is developed for data retiming. Occupying a footprint of 0.26 mm × 0.63 mm per lane, the transceiver test chip is packaged in a flip chip ball grid array (FC-BGA) module. Measurement results demonstrate a horizontal eye opening of 38 % at a bit error rate (BER) of 10−12 over a channel with 28 dB loss at 8 GHz. Moreover, the power consumption is 68.85 mW per lane at 16 Gb/s.

High precision low jitter pulse generator implemented with FPGA transceiver

Precisely controlled digital pulse plays a crucial role in various cutting-edge testing applications. This paper introduces an innovative approach to digital pulse generation utilizing an FPGA transceiver, with the AMD evaluation board ZCU102 serving as a demonstrative platform. In the normal mode, the transmitter generates a serial bit stream, enabling the generation of single or repeated pulses with configurable width and period. In the high precision mode, an internal dedicated phase interpolator enhances the configuration step size for width and period by up to 64 times, providing finer phase shift capability. The demonstration system operates at a line rate of 10Gbps, achieving a resolution of 100ps in normal mode and 1.5625ps in high precision mode. This paper details the design methodology, presents test results for pulse width uncertainty and non-linearity, and showcases achieved period jitter and time interval error jitter as small as around 1ps.

Seismic Data Reconstruction Using a Phase-Shift-Plus-Interpolation-Based Apex-Shifted Hyperbolic Radon Transform

The apex-shifted hyperbolic Radon transform (ASHRT) based on the Stolt-stretch operator can be implemented in the frequency domain, which accelerates the computation efficiency of ASHRT. However, the Stolt-stretch operator has limitations when it comes to velocity variations. Therefore, this paper introduces a new ASHRT approach based on post-stack phase shift plus interpolation (PSPI) imaging and modeling operators. This new approach is designed to better adapt to changes in medium velocity and enhance the quality of data reconstruction. When combining this novel transformation with sparsity constraints for model testing and real data applications, the experimental results indicate that it is an effective data reconstruction tool, with superior data reconstruction results compared to traditional ASHRT based on the Stolt-stretch operator.

A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4–8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme enabling continuous data rate support. The digital architecture not only eliminates the large filtering capacitor but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm2 in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. The measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the synchronous optical networking (SONET) OC-192 jitter tolerance mask at least by 0.2 unit interval at high frequencies (4–100 MHz) with a $2^{31}-1$ pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of $10^{-12}$ .

Simplification of Linear Beam-forming Networks by Applying a Novel Phase Interpolation Technique

Simplification of Linear Beam-forming Networks by Applying a Novel Phase Interpolation Technique

Retrospective reconstruction of four-dimensional magnetic resonance from interleaved cine imaging – A comparative study with four-dimensional computed tomography in the lung

Background and purposeImaging of respiration-induced anatomical changes is essential to ensure high accuracy in radiotherapy of lung cancer. We expanded here on methods for retrospective reconstruction of time-resolved volumetric magnetic resonance (4DMR) of the thoracic region and benchmarked the results against 4D computed tomography (4DCT). Materials and methodMR data of six lung cancer patients were collected by interleaving cine-navigator images with 2D data frame images, acquired across the thorax. The data frame images have been stacked in volumes based on a similarity metric that considers the anatomical deformation of lungs, while addressing ambiguities in respiratory phase detection and interpolation of missing data. The resulting images were validated against cine-navigator images and compared to paired 4DCTs in terms of amplitude and period of motion, assessing differences in internal target volume (ITV) margin definition. Results4DMR-based motion amplitude was on average within 1.8 mm of that measured in the corresponding 2D cine-navigator images. In our dataset, the 4DCT motion and the 4DMR median amplitude were always within 3.8 mm. The median period was generally close to CT references, although deviations up to 24 % have been observed. These changes were reflected in the ITV, which was generally larger for MRI than for 4DCT (up to 39.7 %). ConclusionsThe proposed algorithm for retrospective reconstruction of time-resolved volumetric MR provided quality anatomical images with high temporal resolution for motion modelling and treatment planning. The potential for imaging organ motion variability makes 4DMR a valuable complement to standard 4DCT imaging.

Energy efficient phase interpolator based hybrid beamforming architecture for massive MIMO system

Energy efficient phase interpolator based hybrid beamforming architecture for massive MIMO system

A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

A 10–26 Gb/s energy-efficient receiver incorporating a dual-feedback nested loop clock and data recovery circuit (DF-CDR) is proposed. Combining a direct modulation path on voltage-controlled oscillator (VCO) and phase interpolator (PI)-based phase rotator inside a phase locked loop (PLL), it improves high-frequency jitter tolerance by 0.15 UI. An edge-first equalization scheme is proposed to reduce power and hardware overhead of decision feedback equalizers. Meanwhile, it facilitates adaptive equalization of continuous time linear equalizer, and background offset calibration of the receiver frontend. A three-stage latch comparator is adopted to enable high-speed direct feedback equalizer. By applying PRBS-31 test pattern through a 32 dB loss channel, the receiver is error-free and features the best energy efficiency of 103 fJ/b/dB at 26 Gb/s.

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS

This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the time domain, the compact interpolation-based time-to-digital converter (TDC) resolves 4-bit in each SAR cycle with 16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> linear TD interpolation. This scaling-friendly architecture reduces the number of capacitive digital-to-analog converters (CDACs) and voltage-to-time converters (VTCs) significantly, leading to low power, small area, low kickback noise, and small input loading. A cascade current-starved inverter based VTC is used in the second SAR conversion cycle, which improves voltage-to-time gain and ensures speed and linearity. Besides, to reduce the TD interpolation error and eliminate the short-circuit current, a novel phase interpolator is proposed. A two-way time-interleaved 7-bit 3.8-GS/s prototype ADC was fabricated in a 28-nm CMOS, occupying an active area of 0.01 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rm ^2$</tex-math> </inline-formula> . With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.9 and 50.8 dB, respectively. Consuming 7.5 mW at 1.0 V supply, the Walden figure of merit (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rm _w$</tex-math> </inline-formula> ) is 24.4 fJ/conversion-step.

A 2–20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop

A 2–20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop

Low-Power Process and Temperature-Invariant Constant Slope-and-Swing Ramp-Based Phase Interpolator

This article presents a process-and temperature-invariant high-resolution and highly linear low-power phase interpolator (PI) as an enabler for discrete-time spatial signal processors (SSPs) and for various mixed-mode RF transceiver architectures. Using current integration techniques, the proposed PI generates an adaptable constant slope-and-swing ramp signal to achieve significantly lower power suited for multiple antenna elements. Switched-capacitor-based bias generation enables tracking the ramp generator over process, voltage, and temperature enhancing the PI linearity. The 7-bit PI realized in the 65-nm CMOS technology can generate full delay range with a resolution of 4.88 ps at 1.6-GHz input frequency. The PI consumes a power of 503 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W and occupies an active area of 0.021 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> with a jitter of 0.410 ps for a 1.6-GHz operation and measured DNL and INL of 0.52 and 0.52 LSB, respectively.

An 8-bit 1.24 mW Sub-1ps DNL Sub-1V Supply Inverter-Based Phase Interpolator Using a PVT-Tracking Adaptive-Bias Circuit

This paper presents an 8-bit inverter-based phase interpolator (PI) using a PVT-tracking adaptive-bias (AB) circuit. The AB circuit preserves the linearity of the PI for the PVT variation. The measured DNL of the PI is 0.4 LSB (0.78 ps). Fabricated in an 8 nm FinFET technology, the PI consumes a power of 1.24 mW and occupies an area of 0.035 mm.

Phase shift plus interpolation with uncorrelated anisotropic parameters

Seismic imaging methods such as phase shift plus interpolation achieve computational efficiency by reducing the associated P-wave velocity model to a small set of reference values. Anisotropy complicates this reduction because multiple parameters characterize an anisotropic model, and they do not necessarily correlate in space. Rather than attempting to find reference parameters for potentially uncorrelated anisotropic models, I find a set of reference traveltimes based on the spatial variation of horizontal slowness at the evanescent boundary. Strong changes in that horizontal slowness mark zones of strong changes in the combined effect of the anisotropic parameters simultaneously, and I use these zones to define the set of reference traveltimes. Based on traveltime comparisons and impulse responses, I find that reference traveltimes rather than reference parameters return greater accuracy with a more reasonable computational cost.

Authentication and encryption protocol with revocation and reputation management for enhancing 5G-V2X security

This paper presents a novel robust solution for key management, message encryption, and authentication, offering enhanced security for 5G-V2X communication. By incorporating bilinear pairing, and AES encryption, the protocol achieves a high level of security. The protocol consists of two key phases: key management and distribution, and message authentication and encryption. In the key management phase, secret sharing and polynomial interpolation techniques are used to generate and distribute the master secret key. The message authentication and encryption utilize bilinear pairing for integrity and origin authentication and symmetric encryption for confidentiality. To address the real-time update limitations of traditional revoking approaches, a reputation-based vehicle revocation mechanism is proposed. This mechanism allows fair revoking based on reputation scores and authenticated feedback, ensuring effective resource management. The proposed protocol utilizes the MIRACL library to implement the bilinear pairing operations. Comparative analysis demonstrates the superior performance of the protocol compared to other bilinear pairing protocols. The results show that the proposed protocol enhances authentication and encryption while incurring short times for message signing and verification (1.925 ms and 7.115 ms, respectively). Furthermore, the protocol supports signature aggregation using bilinear properties, resulting in constant verification time regardless of the number of signatures.

Improving Linearity in CMOS Phase Interpolators

Improving Linearity in CMOS Phase Interpolators

28 Gbaud PAM-4 Burst-Mode CDR With Reconfigurable Sampling Scheme

This paper presents a fast-locking 28 Gbaud PAM-4 CDR targeting for burst-mode operation. By implementing an oversampling scheme tailored for the preamble stage signal according to the pattern appearance regulation, the trade-off between the loop bandwidth and the convergence time in the conventional CDR is avoided. In addition, to reduce power consumption in the oversampling mode, a 3-phase sampling scheme equivalent to 3 times-oversampling with a minimal phase shift range of 30 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> is proposed. The PAM-4 burst-mode CDR also includes a conventional Bang-Bang phase locking loop with a bandwidth of 5 MHz. Realized in a 65nm bulk CMOS technology, the CDR chip achieves 28 Gbaud PAM-4 burst-mode clock recovery within 10 ns. With integrating slicers, phase interpolators and output buffers, the total power consumption of the CDR is 154 mW. Compared with the prior arts, to the best of authors’ knowledge, the proposed CDR first achieves on-chip phase-locking with PAM-4 Burst signals, based on the proposed PAM-4 burst-mode signal tailored 3-phase oversampling scheme.

A Very High Linearity Twin Phase Interpolator With a Low-Noise and Wideband Delta Quadrature DLL for High-Speed Data Link Clocking

A twin phase-interpolator (PI) architecture cancels most of the deterministic phase nonlinearity and achieves very high linearity across a wide frequency range with only four-phase input clocks. A delta quadrature delay-locked loop (Delta QDLL) is further proposed that generates wideband, low-jitter, and accurate quadrature clocks from the delay difference of two paths with a background analog quadrature tuning loop. A 1.2-V 65-nm CMOS prototype has a Delta QDLL with a quadrature accuracy of 0.9° from 3.5 to 11 GHz across ten chip samples. It consumes 7.8 mW at 7 GHz and has a 48.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {fs}_{\mathbf {rms}}$ </tex-math></inline-formula> jitter, yielding an outstanding figure of merit of −257.4 dB. The 7-bit twin PI achieves a less-than-1.45-LSB peak-to-peak integral nonlinearity ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {INL}_{\mathbf {pp}}$ </tex-math></inline-formula> ) from 3.5 to 11 GHz and the lowest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {INL}_{\mathbf {pp}}$ </tex-math></inline-formula> of 0.72 LSB at 7 GHz. The PI has a 58.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {fs}_{\mathbf {rms}}$ </tex-math></inline-formula> jitter for a fixed PI control code. At 7 GHz with −1429-ppm clock modulation, the integrated fractional spur is as low as −41.7 dBc.