Abstract
The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more clock generators with increased performance (frequency and jitter) and lower power budgets. The traditional current mode low swing clock generators were used widely in industry about 10 years ago. Although it had the advantage of higher supply noise rejection due to the differential nature of the architectures, however, it had the disadvantages of high-power consumption, large layout area, and not friendly to process scaling. Contrary to current mode low swing design, clock generator architectures with CMOS large swing signaling, which have advantages of low power consumption, small area, and based on circuits friendly to process scaling, have been widely adopted for clocking generation in the industry since 2009. In this paper, phase locked loops, delay locked loops, phase interpolators, high resolution digital to time converter and clock distribution techniques with CMOS large swing signaling will be discussed and reviewed.
Highlights
Abstract--The requirement for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drives the needs for more clock generators with increased performance and lower power budgets
Cost concerns dictate that these clock generator circuits, such as phase locked loops (PLL), delay locked loop (DLL), phase interpolators (PI), and clock or clock-phases distribution networks, must meet all performance specifications in standard CMOS technology without adding additional process cost
The traditional current mode low swing clock circuits were widely used in phase locked loops [3,4], delay locked loops [2,4,5,6,7], clock-data-recovery (CDR) and phase interpolators [8,9,10,11] until about 10 years ago
Summary
Due to the increasing bandwidth demands of data centers, multi-core computers, cell phones, and other IoT devices, energy-efficient high-speed clock generators are necessary in today’s computing systems. The traditional current mode low swing clock circuits were widely used in phase locked loops [3,4], delay locked loops [2,4,5,6,7], clock-data-recovery (CDR) and phase interpolators [8,9,10,11] until about 10 years ago They had the advantage of higher power supply noise rejection due to the differential nature of the design, they had the disadvantages of high-power consumption, large layout area, and being not friendly to process scaling. Several other phase interpolators employing CMOS large supply swing signaling were published [14,15,16,17,18] for use in high speed IOs, multiplying delay locked loops (MDLL), and digital to time converter (DTC) circuits.
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