Phase Interpolation Research Articles

Step Surface Profile Measurement Based on Fringe Projection Phase-Shifting Using Selective Sampling

Fringe projection is a non-contact optical method that is widely used in the optical precision measurement of complex stepped surfaces. However, the accuracy of the fringe phase extraction employed has a direct impact on the measurement precision of the surface shape. Where phase-shifting measurement is used, the classical equal step phase extraction algorithm can only be used to measure simple and smooth surfaces, and leads to measurement errors on complex stepped surfaces, which affects the accuracy of the phase extraction. In addition, the iterative process lasts for a long time, resulting in a low efficiency. This paper proposes a step-by-step phase-shifting extraction algorithm based on selective sampling to measure the contour of the stepped surface. Firstly, the fringe pattern is sampled at equal intervals to reduce the iterative calculation time. Finally, the accurate measurement phase is calculated by the alternating iteration method. The phase extraction accuracy and iteration times are compared in experimental measurements between classical iterative algorithms such as four-step phase-shifting algorithms and the variable phase shift phase interpolation algorithm based on selective sampling. It is shown that the variable frequency phase-shifting extraction algorithm based on selective sampling has a shorter operation time, smaller error, and higher accuracy than the traditional iterative algorithm in fringe projection measuring complex stepped surfaces.

A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving −110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp

A phase interpolator (PI)-free fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> sampling phase-locked loop (SPLL) has been proposed and implemented in 130 nm CMOS technology, which eliminates time-domain PI, digital-to-time converter (DTC), or background calibration. This phase-locked loop (PLL) employs two linear slope generators (LSGs) to produce linear waveforms, which are related to the VCO feedback phase. Then the reference directly samples the LSG outputs to obtain the phase error. Following this, a 3 bit DAC-based phase interpolating charge pump (PICP) is utilized to interpolate the phase error before feeding it to the loop filter. This enables the SPLL to achieve a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> ratio without any DTC or calibration. On-chip frequency-modulated continuous-wave (FMCW) chirp generation is also included, which provides 500 MHz FMCW chirp with reconfigurable chirp rate and up to 25% chirp bandwidth to carrier frequency ratio. It consumes 2.8 mW from a 1.2 V supply and occupies an active area of about 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With a 50 MHz crystal reference, the in-band phase noise is measured to be 109 dBc/Hz at 200 kHz offset. The FoM for the system is measured as −243~ −247.5 dB.

A 4-Element Digital Modulated Polar Phased-Array Transmitter With Phase Modulation Phase-Shifting

A novel architecture of a digital modulated polar phased-array transmitter with phase modulation (PM) phase-shifting and feed-forward controlled dynamic matching (FFCDM) is presented in this article. Phase-shifting in a PM signal path is utilized in each element, which shares many components including a phase modulator, baseband, and IF components. The characteristics of the proposed architecture are analyzed. With a constant envelope of PM signals, the implicit nonlinearity of the phase shifter in this architecture has low impact on the linearity performance of a phased-array system. Meanwhile, low phase error can be achieved by high-resolution phase interpolation with the digital predistortion (DPD) technique. Efficiency for both saturated and 6-dB back-off power is enhanced by digital power amplifier (DPA) with FFCDM. As a proof of concept, a 3–7 GHz 4-element phased-array transmitter is designed and fabricated in 40-nm CMOS based on the proposed method. The measured root-mean-square (rms) phase error of 0.3°, effective phase shifting resolution of 9-bit, and peak system efficiency of 38.2% are achieved. For 40 MHz 64-QAM modulation signal, it exhibits EVM of 5.38% and 5.37%, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {out}}$ </tex-math></inline-formula> of 14.30 and 14.46 dBm, and PAPR of 7.08 and 6.97 at 3.5 and 5.2 GHz, respectively. The measured peak EIRP is 35.6 dBm with a unit antenna gain of 2.98 dBi at 5 GHz. The radiation patterns with 0°, 15°, 30°, and 45° steering are measured based on monopole antennas. Meanwhile, the array achieves < 4.7% and < 5.9% EVM for 64-QAM signals with bandwidths of 20 and 40 MHz, respectively.

A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator.

Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption.

Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation

This article proposes compact expressions for the jitter in clock and data recovery (CDR) circuits based on bang-bang phase detector including the phase noise of the transmitter and receiver oscillators as well as the quantization noise associated with the finite number of phases of the phase interpolator (PI) that align the receiver clock to the incoming data. Different approaches to perform the Early/Late detection on deserialized data and edge samples are compared: the use of majority voting degrades the CDR bandwidth, increasing the impact of the clock jitter on the CDR jitter; on the other hand, counting the single Early/Late occurrences does not degrade the bandwidth but increases the noise related to the finite phases of the PI. The proposed analytical formulas are validated against event-driven behavioral simulations of the CDR system including free-running oscillators as well as phase-locked loop (PLL) for clock generation.

A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation

This brief presents a bidirectional nonlinearly coupled quadrature voltage-controlled oscillator (BNC-QVCO) incorporating passive phase interpolation for the generation of multiphase signals. In addition, to generate multiphase signals, the proposed bidirectional nonlinearly coupling network improves the phase noise performance of the QVCO by producing approximate-in-phase injection-coupling currents into the LC tank. Moreover, to balance the amplitude of eight-phase signals, an additional passive amplitude division circuit is implemented with capacitor banks for calibration. For verification, a BNC-QVCO incorporating passive phase interpolation is implemented in a 40-nm CMOS technology with a core area of 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured multiphase signals achieve a phase noise of -116.57 dBc/Hz at 1-MHz offset from 4.32 GHz. The power consumption without buffers is 10.2 mW under 1-V supply voltage and a 20% frequency tuning range from 4 to 4.8 GHz is achieved with the implemented digitally controlled capacitor banks.

A Clock Distribution and Synchronization Scheme Over Optical Links for Large-Scale Physics Experiments

In large-scale physics experiments, there is a trend to implement clock distribution and synchronization over multi-Gigabit serial links on optical networks. The accuracy of clock synchronization in such a fashion is mainly determined by two aspects: one is the stability of the clock distribution over the links, and the other is the employed mechanism of clock synchronization. To achieve a high synchronization accuracy in a range of tens of picoseconds, this article proposes a new optical fiber link and synchronization scheme based on optical circulators and serial transceivers embedded in field-programmable gate arrays (FPGAs). Benefiting from the single wavelength fiber connection, high-precision time-to-digital converters (TDCs) and phase interpolator (PI) sub-block in state-of-the-art Serializer-Deserializer (SerDes) transceivers on FPGAs, the offset of distributed clocks can be measured on-line and precisely compensated. The time synchronization performance is evaluated on a prototype system with three levels of structure. Through multiple power or reset cycles and long-term operation tests, the clock synchronization accuracy over a 5-km fiber connection is measured to be lower than 15 ps, and the recovered clocks at nodes at different levels have independent jitter, all lower than 4.2 ps. In addition, the achieved high performance is also proved to be insensitive to operating temperature and the connection distance.

A CMOS implementation of controller based all digital phase locked loop (ADPLL)

PurposeBiomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose of this paper is to the design of controller-based all-digital phase-locked loop (ADPLL) in a 45 nm CMOS process.Design/methodology/approachInitially, an open-loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved.FindingsThe designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of −98.36 at 1-MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 µW.Research limitations/implicationsA time to digital converter (TDC)-less controller-based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 µW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of −98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC.Social implicationsThe designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society.Originality/valueThe implementation of open-loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power.

A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL

Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs) for the Internet-of-Things (IoT). One recurrent issue with clock generators is multiple-phase generation, especially for low-power applications; several methods of phase generation have been proposed, one of which is phase interpolation. We propose a phase interpolator (PI) that employs the concept of constant-slope operation. Consequently, a low-power highly-linear operation is coupled with the wide dynamic range (i.e., phase wrapping) capabilities of a PI. Furthermore, the PI is powered by a low-dropout regulator (LDO) supporting fast transient operation. Implemented in 65-nm CMOS technology, it consumes 350μW at a 1.2-V supply and a 0.5-GHz clock; it achieves energy efficiency 4x - 15x lower than state-of-the-art (SoA) digital-to-time converters (DTCs) and an integral non-linearity (INL) of 2.5x-3.1x better than SoA PIs, striking a good balance between linearity and energy efficiency.

Low Power Clock Generator Design With CMOS Signaling

The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more clock generators with increased performance (frequency and jitter) and lower power budgets. The traditional current mode low swing clock generators were used widely in industry about 10 years ago. Although it had the advantage of higher supply noise rejection due to the differential nature of the architectures, however, it had the disadvantages of high-power consumption, large layout area, and not friendly to process scaling. Contrary to current mode low swing design, clock generator architectures with CMOS large swing signaling, which have advantages of low power consumption, small area, and based on circuits friendly to process scaling, have been widely adopted for clocking generation in the industry since 2009. In this paper, phase locked loops, delay locked loops, phase interpolators, high resolution digital to time converter and clock distribution techniques with CMOS large swing signaling will be discussed and reviewed.

A 12-Bit 0.5–2.4-GHz 0.65°-Peak-INL Parasitic-Insensitive Digital-to-Phase Converter

A 12-bit 0.5–2.4-GHz parasitic-insensitive digital-to-phase converter (DPC) with high linearity is presented in this letter. A modified parasitic-insensitive charge-based (PICB) phase interpolator (PI) is proposed to avoid linearity degradation caused by parasitic effect. A novel PI cell with separated clock selecting logic is implemented to solve charge leakage and overcharging problem. The DPC is designed and fabricated in 40-nm CMOS technology, which occupies a chip area of 0.04 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 18.3 mW from a 1.3-V supply voltage. Operating in a frequency range from 0.5 to 2.4 GHz, the DPC demonstrates a peak integral nonlinearity (INL) of 0.65° and a peak differential nonlinearity (DNL) of 0.25°.

Fast Digital Clock Calibration of a Differential 6.4 Gb/s/pin Bidirectional Asymmetric Memory Interface

A differential 6.4 Gb/s/pin bidirectional asymmetric memory interface with a fast all-digital clock calibration method is presented. The proposed clock calibration reduces the link training time of the interface compared to the conventional data eye detection by eliminating the need to sweep the receiver clock phase. Instead a scalable synthesized phase-to-digital converter (PDC) is used to measure the offset from the ideal 90° shift while a clock pattern is transmitted. Phase interpolator nonlinearity is compensated in an additional adjustment step in order to minimize the clock centering error. A prototype ASIC which can be configured to act as either a controller or a memory device was fabricated in a 65nm CMOS process and tested. The measured read and write training durations are 3.1 $\mu \text{s}$ and 3.3 $\mu \text{s}$ , respectively. The additional area required for the PDC in each transceiver is 0.004mm2.

A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop

This paper presents a high speed dual channel 12.5 Gbps receiver for serial link communication. Each channel consists of a continuous time linear equalizer (CTLE), a novel 12.5 Gbps dual loop clock and data recovery (CDR) circuit based on phase interpolation with only simple CML and CMOS logic, which makes the design simplicity and more tolerant to process, voltage and temperature variations. A single PLL shared by the two channel CDRs generates quadrature clock phases and distributes high frequency clock to each CDR for data recovery. The 12.5 Gbps two channel receiver prototype was designed in 65-nm CMOS technology with phase interpolation based digital locked loop, occupying an active area of 1.3 mm2 and consuming a power of 300 mW from a 1.2 V power source.

A 2–24-GHz 360° Full-Span Differential Vector Modulator Phase Rotator With Transformer-Based Poly-Phase Quadrature Network

This article presents a differential vector modulatorbased phase rotator (PR) performing 360° full-span phase interpolation over a first-ever decade-wide instantaneous bandwidth from 2 to 24 GHz. The proposed PR employs a three-stage transformer poly-phase network with high-precision and ultrawide-bandwidth, two highly linear 5-bit variable gain amplifiers (VGAs), a differential series-shunt-series inductor peaking load network for bandwidth extension and an open-drain buffer. It is implemented in a standard 65-nm bulk CMOS process with a chip area of 1.2 mm x 1.8 mm. The measurement results demonstrate the maximum rms quantization phase error of 1.22° within a 1.5-dB output magnitude variation for full 360° interpolations from 2 to 24 GHz and the -3-dB magnitude bandwidth is up to 19 GHz, respectively. Moreover, due to the wideband high-quality in-phase/quadrature (I/Q) signal generation and high-precision I/Q interpolation of the VGAs, the PR can perform full-span phase synthesis with a constant set of phase shift code settings for all the operating frequencies. For interpolating 22.5°/15° phase step over the 360° full-span, the “one-code” setting operation achieves an rms phase error of 1.56°/1.42° from 3.5 to 22.5 GHz without any frequency-dependent code/look-up table (LUT), tunable element, or band-selection switch. Furthermore, with the “one-code” setting operation, the modulation tests demonstrate measured rms error-vector-magnitude (EVM) values below 5% for a 50-kSym/s QPSK signal from 3.3 to 22.3 GHz and for a 16-quadratic-amplitude modulation (QAM) signal from 2.7 to 22 GHz.

Four-Element Wide Modulated Bandwidth MIMO Receiver With &gt;35-dB Interference Cancellation

Active control of interference is necessary with increased cell density, more complicated environmental reflections, and coexistence of multiple networks for next-generation wireless communications. The existing radio receiver architectures for spatial interference cancellation (SpICa) are limited by the spatial nulls created by a phased-antenna array (PAA) and cannot cover wide modulated bandwidths (BWs). We propose a discrete-time-delay-compensating technique for canceling spatial interferences with wide modulated BWs to reduce the dynamic range requirement for the data converter. Integral to the proposed circuit is a switched-capacitor-based multiply-and-accumulate processor that incorporates a reconfigurable phase interpolator and time interleaver for precise digitally tunable delays and multiplication of the input signal to an orthogonal matrix. The digital time interleaver enables 5-ps resolution with a reconfigurable range up to 15 ns. The measured results demonstrate greater than 35-dB SpICa over 80-MHz modulated BWs in the 65-nm CMOS with 52 mW of power consumption.

Computational modeling of charge hopping dynamics along a disordered one-dimensional wire with energy gradients in quantum environments.

This computational study investigates the effects of energy gradients on charge hopping dynamics along a one-dimensional chain of discrete sites coupled to quantum bath, which is modeled at the level of Pauli master equation (PME). This study also assesses the performance of different approximations for the hopping rates. Three different methods for solving the PME, a fourth order Runge-Kutta method, numerical diagonalization of the rate matrix followed by analytic propagation, and kinetic Monte Carlo simulation method, are tested and confirmed to produce virtually identical values of time dependent mean square displacement, diffusion constant, and mobility. Five different rate expressions, exact numerical evaluation of Fermi's Golden Rule (FGR) rate, stationary phase interpolation (SPI) approximation, semiclassical approximation, classical Marcus rate, and Miller-Abrahams rate, are tested to help understand the effects of approximations in representing quantum environments in the presence of energy gradients. The results based on direct numerical evaluation of FGR rate exhibit transition from diffusive to non-diffusive behavior with the increase in the gradient and show that the charge transport in the quantum bath is more sensitive to the magnitude of the gradient and the disorder than in the classical bath. Among all the four approximations for the hopping rates, the SPI approximation is confirmed to work best overall. A comparison of two different methods to calculate the mobility identifies drift motion of the population distribution as the major source of non-diffusive behavior and provides more reliable information on the contribution of quantum bath.

Pre-Calibration of the Phase Interpolator of a Precision Time Interval Meter

Pre-Calibration of the Phase Interpolator of a Precision Time Interval Meter

1–3-GHz Self-Aligned Open-Loop Local Quadrature Phase Generator With Phase Error Below 0.4°

The circuit architecture to generate differential CMOS quadrature (I/Q) local oscillator (LO) signals from a differential input at the same frequency is presented. The circuit features an open-loop implementation, which relies on two matched delays and linear phase interpolation. The feasibility of this approach is demonstrated by implementing an I/Q generator covering the operating frequency range from 1 to 3 GHz, manufactured in a 28-nm bulk-CMOS process. The optimum phase accuracy is better than ±0.4° for the entire measured frequency region. A phase noise performance of -163.2 dBc/Hz at 100-MHz offset is achieved at 2 GHz with a power consumption of only 4.4 mW from a 1.1-V supply.

A Picosecond-Resolution Digitally-Controlled Timing Generator With One-Clock-Latency at Arbitrary Instantaneous Input

This brief presents an open-loop all-digital burst-mode digital-to-time converter (DTC). The output timing is converted in one-clock latency in response to any instant change of input which is a time range with a digital code. The given time range is coarsely estimated using a ring oscillator based edge-counting. It is then processed with a self-referenced phase interpolation which greatly reduces the actual input range for interpolation and achieves a good linearity in the whole conversion range. The implemented DTC in 28nm LP CMOS shows the maximum peak INL error of 5.34ps in a seamless conversion range of from 16ps to 2850ps.

A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR

A 100 Gb/s quad-lane SerDes receiver with a phase-interpolator (PI)-based quarter-rate all-digital clock and data recovery (CDR) is presented. The proposed CDR utilizes a multi-phase multiplying delay-locked loop (MDLL) to generate the eight-phase reference clocks, which achieves multi-phase frequency multiplication with a small area and less power consumption. The shared MDLL generates and distributes eight-phase clocks to each CDR. The proposed CDR uses a new initial phase tracker that uses a preamble to achieve a fast lock time of about 12 ns and to provide a constant output data sequence. The CDR utilizes quarter-rate 2x-oversampling architecture, and the PI controller is designed full custom to minimize the loop latency. To improve the dithering jitter performance of the recovered clock, the decimation factor of the CDR can be adjustable. Also, a new continuous-time linear equalizer (CTLE) receiver was adopted to reduce power consumption and achieved a data rate of 25 Gb/s/lane. The proposed SerDes receiver with a digital CDR is implemented in 40 nm CMOS technology. The 100 Gb/s four-channel SerDes receiver (4 CTLEs + 4 CDRs + MDLL) occupies an active area of only 0.351 mm2 and consumes 241.8 mW, which achieves a high energy efficiency of 2.418 pJ/bit.