Phase Change Memory Devices Research Articles

Reliability modeling and analysis of flicker noise for pore structure in amorphous chalcogenide-based phase-change memory devices

Phase-change memory (PCM) devices are one of the most promising memory devices to replace the flash memory devices in terms of both scalability and performances. However, typically high programming current to operate devices is a fatal problem in comparison with flash memory. Therefore, many studies have been investigated by changing the contact area and optimizing the structure. In addition, in perspective of characteristic of reliability, the drift and noise are the important problem to degrade the characteristic of devices and the flicker noise is one of the crucial factors in amorphous chalcogenide-based PCM devices. In this paper, we examined the pore-like structure, which is one of the promising structures having small reset current, comparing with conventional mushroom structure by the device reliability analysis for flicker noise using TCAD modeling and simulation.

Microstructure-dependent DC set switching behaviors of Ge–Sb–Te-based phase-change random access memory devices accessed by in situ TEM

Phase-change random access memory (PCRAM) is one of the most promising nonvolatile memory devices. However, inability to secure consistent and reliable switching operations in nanometer-scale programing volumes limits its practical use for high-density applications. Here, we report in situ transmission electron microscopy investigation of the DC set switching of Ge–Sb–Te (GST)-based vertical PCRAM cells. We demonstrate that the microstructure of GST, particularly the passive component surrounding the dome-shaped active switching volume, plays a critical role in determining the local temperature distribution and is therefore responsible for inconsistent cell-to-cell switching behaviors. As demonstrated by a PCRAM cell with a highly crystallized GST matrix, the excessive Joule heat can cause melting and evaporation of the switching volume, resulting in device failure. The failure occurred via two-step void formation due to accelerated phase separation in the molten GST by the polarity-dependent atomic migration of constituent elements. The presented real-time observations contribute to the understanding of inconsistent switching and premature failure of GST-based PCRAM cells and can guide future design of reliable PCRAM. Using in situ electron microscopy, researchers in Korea have discovered why phase-change memory devices can fail during switching operations. Phase-change materials, such as germanium–antimony–tellurium (Ge–Sb–Te) alloys, rapidly switch between crystalline and amorphous phases on electrical heating. Researchers have used this to make memory chips that are hundreds of times faster than flash devices, but inconsistent performance currently limits practical, high-density applications. Sang Ho Oh from Pohang University of Science and Technology and colleagues observed the phase changes of Ge–Sb–Te memory cells in real time by applying direct-current voltages through a transmission electron microscope. They found that the device lifetime critically depended on the atomic microstructure around the active switching site. Ironically, higher degree of crystallinity of this passive zone can cause more excessive heat dissipation, leading to eventual melting and evaporation of cells. Applying in situ TEM techniques to GST-based vertical PCRAM cells, we directly observed the DC set switching process of real devices for the first time. The results show that the microstructure of crystalline GST matrix is an important structural parameter determining the local temperature distribution. In the case of highly crystallized GST matrix, the device failure occurred via two-step void formation due to the polarity-dependent electromigration.

Three dimensional finite element modeling and characterization of intermediate states in single active layer phase change memory devices

The high contrast in the electrical resistivity between amorphous and crystalline states of a phase change material can potentially enable multiple memory levels for efficient use of a data storage medium. We report on our investigation of the role of the current injection site geometry (circular and square) in stabilizing such intermediate states within a nanoscale single-phase change material system (Ge2Sb2Te5). We have developed a three dimensional multiphysics model, which includes phase change kinetics, electrical, thermal, thermoelectric, and percolation effects, all as a function of temperature, using an iterative approach with coupled differential equations. Our model suggests that the physical origin of the formation of stable intermediate states in square top contact devices is mainly due to anisotropic heating during the application of a programming current pulse. Furthermore, the threshold current requirement and the width of the programming window are determined by crystallite nucleation and growth rates such that a higher crystallization rate leads to a narrower range of current pulses for switching to intermediate resistance level(s). The experimentally determined resistance maps, those that are indicative of the crystallinity, show good agreement with the simulated phase change behavior confirming the existence of stable intermediate states. Our model successfully predicts the required programming conditions for such mixed-phase levels, which can be used to optimize memory cells for future ultra-high density data storage applications.

Vacuum-Insulated Self-Aligned Nanowire Phase-Change Memory Devices

Phase-change memory (PCM) is an emerging technology for faster nonvolatile memory where a small volume of phase-change material is switched between amorphous and crystalline states to provide distinct logic levels. A major difficulty with these devices is the high-power requirement for set and reset operations. In this brief, we computationally analyze a vacuum-insulated self-aligned Ge2Sb2Te5 nanowire (NW) PCM device and propose a way to control the placement and orientation of the NWs. The analysis is performed using 2-D rotationally symmetric finite-element simulations with temperature-dependent material parameters and accounting for thermoelectric effects. Simulation results predict a $\sim 10\times $ reduction in current required for reset operation and minimal thermal crosstalk when compared with a similarly sized conventional mushroom cell due to effective suppression of lateral heat loss. The operation of the vacuum-insulated NW devices is also almost independent of current polarity (unlike that of the mushroom cell), which can be advantageous for more flexible array programming schemes. These devices can be used to build densely packed PCM with lower power consumption and less thermal crosstalk.

Field-Induced Nucleation in the Presence of a Metal Electrode

The operation of tomorrow's phase-change and resistive memory devices is based on the electric-field-induced nucleation of conducting particles embedded in an insulating host. The authors show how that process is exponentially accelerated in the presence of metal electrodes, because of the energy decrease due to image-charge attraction. Their insight should help to shape these emerging technologies.

Ti–Sb–Te Alloy: A Candidate for Fast and Long-Life Phase-Change Memory

Phase-change memory (PCM) has great potential for numerous attractive applications on the premise of its high-device performances, which still need to be improved by employing a material with good overall phase-change properties. In respect to fast speed and high endurance, the Ti-Sb-Te alloy seems to be a promising candidate. Here, Ti-doped Sb2Te3 (TST) materials with different Ti concentrations have been systematically studied with the goal of finding the most suitable composition for PCM applications. The thermal stability of TST is improved dramatically with increasing Ti content. The small density change of T0.32Sb2Te3 (2.24%), further reduced to 1.37% for T0.56Sb2Te3, would greatly avoid the voids generated at phase-change layer/electrode interface in a PCM device. Meanwhile, the exponentially diminished grain size (from ∼200 nm to ∼12 nm), resulting from doping more and more Ti, enhances the adhesion between phase-change film and substrate. Tests of TST-based PCM cells have demonstrated a fast switching rate of ∼10 ns. Furthermore, because of the lower thermal conductivities of TST materials, compared with Sb2Te3-based PCM cells, T0.32Sb2Te3-based ones exhibit lower required pulse voltages for Reset operation, which largely decreases by ∼50% for T0.43Sb2Te3-based ones. Nevertheless, the operation voltages for T0.56Sb2Te3-based cells dramatically increase, which may be due to the phase separation after doping excessive Ti. Finally, considering the decreased resistance ratio, TixSb2Te3 alloy with x around 0.43 is proved to be a highly promising candidate for fast and long-life PCM applications.

Femtosecond laser-induced crystallization of amorphous N-doped Ge8Sb92 films and in situ characterization by coherent phonon spectroscopy

Femtosecond laser-irradiation-induced phase change of amorphous N-doped Ge8Sb92 films is in situ studied by coherent phonon spectroscopy. We have observed that a new coherent optical phonon (COP) mode occurs as laser irradiation fluence reaches certain thresholds, indicating laser-induced phase changes. Additionally, this new phonon mode has also been verified in heat-annealing-crystallized N-doped Ge8Sb92 films, confirming the emergence of laser-irradiation-induced crystallization. By measuring the pump fluence dependence of COP dynamics in laser-crystallized N-doped Ge8Sb92 films, we found that the frequency and lifetime of COP decrease with the increasing of pump fluence, which suggests good crystallinity in laser-crystallized N-doped Ge8Sb92 films. It has also been observed that the crystallization temperature of amorphous N-doped Ge8Sb92 films increases with N-doping content. Our results indicate promising applications of N-doped Ge8Sb92 films in optical phase-change memory devices.

Flexible one diode-one phase change memory array enabled by block copolymer self-assembly.

Flexible memory is the fundamental component for data processing, storage, and radio frequency communication in flexible electronic systems. Among several emerging memory technologies, phase-change random-access memory (PRAM) is one of the strongest candidate for next-generation nonvolatile memories due to its remarkable merits of large cycling endurance, high speed, and excellent scalability. Although there are a few approaches for flexible phase-change memory (PCM), high reset current is the biggest obstacle for the practical operation of flexible PCM devices. In this paper, we report a flexible PCM realized by incorporating nanoinsulators derived from a Si-containing block copolymer (BCP) to significantly lower the operating current of the flexible memory formed on plastic substrate. The reduction of thermal stress by BCP nanostructures enables the reliable operation of flexible PCM devices integrated with ultrathin flexible diodes during more than 100 switching cycles and 1000 bending cycles.

Threshold switching uniformity in In2Se3 nanowire-based phase change memory**Project supported by the National Basic Research Program of China (Grant No. 2011CBA00604).

The uniformity of threshold voltage and threshold current in the In2Se3 nanowire-based phase change memory (PCM) devices is investigated. Based on the trap-limited transport model, amorphous layer thickness, trap density, and trap depth are considered to clarify their influences upon the threshold voltage and threshold current through simulations.

Hierarchically Self-Assembled Block Copolymer Blends for Templating Hollow Phase-Change Nanostructures with an Extremely Low Switching Current

Phase change memory (PCM) is one of the most promising candidates for next-generation nonvolatile memory devices because of its high speed, excellent reliability, and outstanding scalability. However, the high switching current of PCM devices has been a critical hurdle to realize low-power operation. Although one solution is to reduce the switching volume of the memory, the resolution limit of photolithography hinders further miniaturization of device dimensions. In this study, we employed unconventional self-assembly geometries obtained from blends of block copolymers (BCPs) to form ring-shaped hollow PCM nanostructures with an ultrasmall contact area between a phase-change material (Ge2Sb2Te5) and a heater (TiN) electrode. The high-density (approximately 0.1 terabits per square inch) PCM nanoring arrays showed extremely small switching current of 2–3 μA. Furthermore, the relatively small reset current of the ring-shaped PCM compared to the pillar-shaped devices is attributed to smaller switching volume, which is well supported by electro-thermal simulation results. This approach may also be extended to other nonvolatile memory device applications such as resistive switching memory and magnetic storage devices, where the control of nanoscale geometry can significantly affect device performances.

Reduction of RESET current in phase change memory devices by carbon doping in GeSbTe films

Phase Change Memory (PCM) has been proposed for use as a substitute for flash memory to satisfy the huge demands for high performance and reliability that promise to come in the next generation. In spite of its high scalability, reliability, and simple structure, high writing current, e.g., RESET current, has been a significant obstacle to achieving a high density in storage applications and the low power consumption required for use in mobile applications. We report herein on an attempt to determine the level of carbon incorporated into a GeSbTe (GST) film that is needed to reduce the RESET current of PCM devices. The crystal structure of the film was transformed into an amorphous phase by carbon doping, the stability of which was enhanced with increasing carbon content. This was verified by the small grain size and large band gap that are typically associated with carbon. The increased level of C-Ge covalent bonding is responsible for these enhancements. Thus, the resistance of the carbon doped Ge2Sb2Te5 film was higher than that for an undoped GST film by a factor of 2 orders of magnitude after producing a stable face-centered cubic phase by annealing. As a consequence, the PCM devices showed a significant reduction in RESET current as low as 23% when the carbon content was increased to 11.8 at. %. This can be attributed to the elevated SET resistance, which is proportional to the dynamic resistance of the PCM device, caused by the high resistance due to a carbon doped GST film.

Heterogeneous Crystallization of the Phase Change Material GeTe via Atomistic Simulations

Phase change materials are the active compounds in optical disks and in nonvolatile phase change memory devices. These applications rest on the fast and reversible switching between the amorphous and the crystalline phases, which takes place in the nano domain in both the time and the length scales. The fast crystallization is a key feature for the applications of phase change materials. In this work, we have investigated by means of large scale molecular dynamics simulations the crystal growth of the prototypical phase change compound GeTe at the interface between the crystalline and the supercooled liquid reached in the device upon heating the amorphous phase. A neural network interatomic potential, markedly faster with respect to first-principles methods, allowed us to consider high-symmetry crystalline surfaces as well as polycrystalline models that are very close to the actual geometry of the memory devices. We have found that the crystal growth from the interface is dominant at high temperatures while it is competing with homogeneous crystallization in the melt at lower temperatures. The crystal growth velocity markedly depends on the crystallographic plane exposed at the interface, the (100) surface being kinetically dominant with respect to the (111) surface. Polycrystalline interfaces, representative of realistic conditions in phase change memory devices, grow at significantly slower pace because of the presence of grain boundaries.

A Single and Adjacent Symbol Error-Correcting Parallel Decoder for Reed–Solomon Codes

This paper presents a novel high-speed Reed–Solomon (RS) decoder. The proposed decoder corrects in parallel adjacent and single-symbol errors; moreover, it serially corrects multiple-symbol errors other than adjacent errors. Its operation is based on a novel scheme that extends an existing binary BCH decoder such that a nonbinary RS code can be targeted. The proposed scheme, however, differs from previous schemes in the algorithm and construction of the parallel decoder; the proposed decoder is efficient for multilevel memory systems such as those utilizing phase change memory devices. Simulation results show that the proposed scheme requires a significantly smaller area and lower power than a traditional fully parallelized RS decoder capable of correcting any double-symbol errors in parallel. Furthermore, it is also shown that it requires a smaller area than a parallel error correction scheme using a nonbinary double-error-correcting orthogonal Latin square code.

High thermal stability Sb3Te-TiN2 material for phase change memory application

For phase change memory (PCM) applications, it has been widely accepted that δ phase Sb-Te has fast operation speed and good phase stability. However, the fast growth crystallization mechanism will cause poor amorphous phase stability and overlarge grain size. We introduce TiN2 into δ phase Sb-Te (Sb3Te) to enhance the amorphous thermal stability and refine the grain size. With TiN2 incorporating, the temperature for 10-year data retention increases from 79 °C to 124 °C. And the grain size decreases to dozens of nanometers scale. Based on X-ray photoelectron spectroscopy and transmission electron microscopy results, we knew that nitrogen atoms bond with titanium, forming disorder region at the grain boundary of Sb3Te-TiN2 (STTN). Thus, STTN has a quite different crystallization mechanism from Sb3Te. Furthermore, PCM device based on STTN can realize reversible phase change under 20 ns electrical pulse.

High speed, high temperature electrical characterization of phase change materials: metastable phases, crystallization dynamics, and resistance drift.

During the fast switching in Ge2Sb2Te5 phase change memory devices, both the amorphous and fcc crystalline phases remain metastable beyond the fcc and hexagonal transition temperatures respectively. In this work, the metastable electrical properties together with crystallization times and resistance drift behaviour of GST are studied using a high-speed, device-level characterization technique in the temperature range of 300 K to 675 K.

Chemical Mechanical Polishing Slurry for Amorphous Ge2Sb2Te5

As flash technologies face scaling issues at 32nm and beyond, phase change memory (PCM) emerges as the best performing candidate for scaled non-volatile memories of next generation. To fabricate PCM device with high volume and low power consumption, the structure of PCM has evolved from planar structure to confined cells, which pose challenges for chemical mechanical polishing (CMP) of the phase change material Ge2Sb2Te5 (GST).In this study, we discuss the properties, polishing mechanisms and slurry formulations for amorphous GST. Static etching characteristics and zeta potentials of GST powders are first explored to evaluate the chemical properties of GST. Then the polishing mechanisms of GST at pH 2 and pH 11 are discussed by means of static etching experiments, polishing performance, GST film hardness measurement, GST solubility and open circuit potential test. Finally, our efforts for GST slurry development are described. By a combination effect of inhibitors, in which one can form adsorption layer on GST by carbonyl O and the other one can further protect GST surface by forming hydrogen bond through multiple OH groups, we have overcome the corrosion issue of GST. Meanwhile, by the adsorption of the inhibitor layers on GST surface and extremely low removal rate of oxide film (<0.05nm/min), we have achieved a self-stop GST CMP process with over-polish dishing <8nm and oxide loss <6nm for 60nm GST vias. We have also resolved the issue of particle residue by using our self-formulated post-cleaning solution.

Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

Suppression of thermoelectric Thomson effect in silicon microwires under large electrical bias and implications for phase-change memory devices

We have observed how thermoelectric effects that result in asymmetric melting of silicon wires are suppressed for increasing electric current density (J). The experimental results are investigated using numerical modeling of the self-heating process, which elucidates the relative contributions of the asymmetric thermoelectric Thomson heat (∼J) and symmetric Joule heating (∼J2) that lead to symmetric heating for higher current levels. These results are applied in modeling of the self-heating process in phase-change memory devices. While, phase-change memory devices show a clearly preferred operation polarity due to thermoelectric effects, nearly symmetric operation can be achieved with higher amplitude and shorter current pulses, which can lead to design of improved polarity-invariant memory circuitry.

Low power ovonic threshold switching characteristics of thin GeTe6 films using conductive atomic force microscopy

Minimizing the dimensions of the electrode could directly impact the energy-efficient threshold switching and programming characteristics of phase change memory devices. A ∼12–15 nm AFM probe-tip was employed as one of the electrodes for a systematic study of threshold switching of as-deposited amorphous GeTe6 thin films. This configuration enables low power threshold switching with an extremely low steady state current in the on state of 6–8 nA. Analysis of over 48 different probe locations on the sample reveals a stable Ovonic threshold switching behavior at threshold voltage, VTH of 2.4 ± 0.5 V and the off state was retained below a holding voltage, VH of 0.6 ± 0.1 V. All these probe locations exhibit repeatable on-off transitions for more than 175 pulses at each location. Furthermore, by utilizing longer biasing voltages while scanning, a plausible nano-scale control over the phase change behavior from as-deposited amorphous to crystalline phase was studied.

Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories

New phase-change memory (PCM) devices have low-access latencies (like DRAM) and high capacities (i.e., low cost per bit, like Flash). In addition to being able to scale to smaller cell sizes than DRAM, a PCM cell can also store multiple bits per cell (referred to as multilevel cell, or MLC), enabling even greater capacity per bit. However, reading and writing the different bits of data from and to an MLC PCM cell requires different amounts of time: one bit is read or written first, followed by another. Due to this asymmetric access process, the bits in an MLC PCM cell have different access latency and energy depending on which bit in the cell is being read or written. We leverage this observation to design a new way to store and buffer data in MLC PCM devices. While traditional devices couple the bits in each cell next to one another in the address space, our key idea is to logically decouple the bits in each cell into two separate regions depending on their read/write characteristics: fast-read/slow-write bits and slow-read/fast-write bits. We propose a low-overhead hardware/software technique to predict and map data that would benefit from being in each region at runtime. In addition, we show how MLC bit decoupling provides more flexibility in the way data is buffered in the device, enabling more efficient use of existing device buffer space. Our evaluations for a multicore system show that MLC bit decoupling improves system performance by 19.2%, memory energy efficiency by 14.4%, and thread fairness by 19.3% over a state-of-the-art MLC PCM system that couples the bits in its cells. We show that our results are consistent across a variety of workloads and system configurations.