Peripheral Circuitry Research Articles

A monolithic 16-channels analog array normalizer

A monolithic circuit has been developed which accepts 16 parallel voltage inputs having values which may be as small as 15 mV or as large as 15 V, and generates 16 concurrent output voltages which are in the same ratios as the inputs with a peak amplitude controllable by the user. Response time is in the region of 1 /spl mu/s at full scale. The chip includes provisions for expansion to any number of channels. Operation is from supplies of /spl plusmn/3 to 15 V at a quiescent current of 125 /spl mu/A. Details of the design principles and peripheral circuitry are provided. Measurements of static accuracy and dynamic performance demonstrate that this approach may often simplify preprocessing of signal arrays in pattern-recognition applications.

A four-state ROM using multilevel process technology

A four-state ROM is described which reduces conventional two-state ROM matrix size by 50%. The four states are encoded in the matrix by varying device thresholds using multiple ion implants. This is called multilevel technology. The detection of matrix device type is determined by the length of time required for a linearly ramped word line to rise from 0 V to the point where the matrix device is turned on. Peripheral circuitry has been devised to measure this time period and output the device type as a two-bit binary code. A 128K ROM which incorporates the new multilevel matrix cell has been fabricated in 6-/spl mu/m metal gate technology. Die size of the ROM is 208/spl times/213 mils/SUP 2/.

A CCD color signal separation IC for single-chip color imagers

A CCD color signal separation IC for solid-state imagers with color filter arrays is described. The device simplifies peripheral circuitry and enhances picture qualities such as resolution, color fidelity, and stability for single-chip color imaging systems, by incorporating CCD delay lines, sample-and-hold circuits, and dual clamp circuit. Also described is a new geometry color filter array which is required by the separation IC. Color image corresponding to horizontal resolution of 340 TV lines with no erroneous color has been obtained from the device when used with a 580 × 475 element CCD imager.

A CCD color signal separation IC for single-chip color imagers

A CCD color signal separation IC for solid-state imagers with color filter arrays is described. The device simplifies peripheral circuitry and enhances picture qualities such as resolution, color fidelity, and stability for single-chip color imaging systems by incorporating CCD delay lines, sample-and-hold circuits, and dual clamp circuit. Also described is a color filter array utilizing Bayer geometry, which is used in the separation IC. Color images corresponding to a horizontal resolution of 340 TV lines with no erroneous color have been obtained from the device when used with a 580/spl times/475 element CCD imager.

An advanced SVG technology for 64K junction-shorting PROM's

The memory cell size of the 64 kbit PROM was reduced to 168µm2(0.26 mil2) by using advanced SVG (Shallow V-Groove) isolation and the wafer stepper process. SVG isolation was introduced in 1979 to suppress the SCR latching between two neighboring cells in the 4 kbit junction-shorting PROM. Since then, the cell size has been reduced until it became limited by the widths of word and bit lines. In the 64 kbit PROM, the SVG isolation technology was improved to achieve self-alignment in diffusion, to provide a high breakdown voltage for Schottky diodes, and to increase the flexibility of the mask layout. The size of the peripheral circuitry was thus reduced to allow a smaller cell size and a smaller parasitic capacitance. The memory cell array occupies 45.0 percent of the total die size of 7.14 × 5.28 mm2.

A digital adaptive filter using a memory-accumulator architecture: Theory and realization

This paper presents a novel approach to the construction of an adaptive filter making use of the so-called distributed arithmetic filter architecture originally suggested by Peled and Liu [7] for the realization of fixed response digital frequency filters. The technique uses only the operations of memory access, addition, and scaling, without the need for digital multiplication. Since multiplication is often quoted as the major bottleneck in digital signal processing structures, the system derives considerable advantage by the exclusion of this operation. The paper presents the derivation of a new adaptive algorithm based on this particular hardware structure, although no rigorous theoretical proof of the algorithm convergence properties is given. Computer simulations are included to demonstrate some of the basic operational characteristics of the structure. Finally, results from a hardware prototype, constructed using standard TTL integrated circuits, are presented. This approach differs from contemporary ideas which depend on the use of digital multipliers in either custom VLSI designs or using standard signal processing chips. It offers high-bandwidth operation at low cost using devices which are already in great demand by the computer market. Alternatively, the algorithm is ideal for implementation as a microprocessor-based system which could operate on real-time voice-bandwidth signals with a minimum of peripheral interface circuitry.

An experimental memory cell using edge-junction gates

We have fabricated and successfully operated NDRO memory cells designed with Nb edge-junction interferometers. To our knowledge this represents the first experimental circuits operated with edge-junction devices. The design was mapped from a design for lead-alloy devices. The cell occupies an area of 60μm ×60μm. In conjunction with the memory cell investigation we designed and tested several individual edge-junction gates. These included several geometries of write gates and sense gates (undamped), and several damped gates, which could be used in the peripheral circuitry of a memory. We have found close agreement between our experimental results and the theoretical models, similar to that found previously for planar-junction gates.

A Radiation Hardened Nonvolatile MNOS RAM

A radiation hardened nonvolatile MNOS RAM (SA2998) is being developed at Sandia National Laboratories. The memory organization is 128 × 8 bits and utilizes two p-channel MNOS transistors per memory cell. The peripheral circuitry is constructed with CMOS metal gate and is processed with standard Sandia rad-hard processing techniques. The device requires +10 V and +25 V for operation. The devices have memory retention after a dose-rate exposure of lE12 rad(Si)/s, are functional after total dose exposure of 1E6 rad(Si), and are dose-rate upset resistant to levels of 7E8 rad(Si)/s.

Amorphous-silicon TFT array for LCD addressing

A 64×64 element matrix array of amorphous-silicon thin-film transistors has been fabricated on a glass substrate. Using a drive scheme to simulate a 500-line display, an output voltage of 8.5 V RMS is obtained. This large output voltage is sufficient for an alphanumeric liquid-crystal display using the dyed cholesteric-nematic phase-change effect. The driving voltages for the array are compatible with LOCMOS (18 V) peripheral circuitry.

Single-chip microcomputer for use in automotive instrumentation

A single-chip microcomputer for automotive applications is described, with specially reference to its application to trip computers. The chip is based on a standard chip (the SAB 8021) and includes peripheral circuitry comprising an A/D converter, 4-, 8- and 16-bit counters, keyboard decoder, display driver and low-power time-of-day clock. The standard chip's RAM and ROM capacities are doubled. The article described various working applications in which the single-chip microcomputer has been used, namely in two types of trip computers. The emulation system is also outlined.

EPROM testing — Part II: Application to 16K N-channel devices

This paper shows how the fault models introduced in the parent paper [1] may be applied to a commercial device. After discussion of typical EPROM architecture and circuitry, it is shown that most of the faults are detected by the proposed test sequence; additional tests are suggested to detect those faults in the peripheral circuitry which are not described by the “symmetric decoder fault” model. Although developed with reference to a specific architecture, most of the results of this work have general validity, since the analysed architecture is common to the great majority of available devices.

Realisation of multithreshold threshold-logic gates using charge-coupled devices

A threshold logic gate is described which uses as its core a charge-coupled device. It is shown that the CCD is suitable for this application because of its ability to (a) quantise charge input to a gate, (b) add charge packets from different gates, and (c) permit conditional charge overflow to occur. The peripheral circuitry employs compatible MOSFET circuits, so that the entire gate can be made in integrated circuit form. The gate is voltage programmbale.

A destructive instability in selective high-power amplifiers with bipolar transistors

An oscillation mode is described which, under certain circumstances, can be excited in selective high-power amplifiers with bipolar transistors. This instability can arise after a single saturation of the transistor and does not depend on feedback or parasitic elements. It is caused by the storage time of the transistor after a saturation. Out of the oscillation mechanism it is shown that transistor voltages and currents during this oscillation mode can be manifold the values of the normal operation. On this account, usually one or a few oscillations of this mode destroy the output transistor, either by voltage of current overload. A computation method is shown with stability charts which describe stability conditions of a given amplifier, depending on the values of the elements of the peripheral circuitry.

A 1-µm Mo—poly 64-kbit MOS RAM

This paper describes a 1-µm 64-kbit MOS RAM using Mopoly technology. New 1-µm double-gate technology using molybdenum and polysilicon (Mo-poly technology) is proposed. In this technology, molybdenum and polysilicon are used for word lines and storage capacitor electrodes in the memory cell, respectively. Therefore, the propagation delay in a word line becomes extremely small and memory cell size is reduced. New two step annealing was developed for stabilizing an Mo-gate MOS structure. Design is optimized for 1-µm Si-gate FET's in peripheral circuitry. A 1-µm Mo-poly 64-kbit MOS RAM was experimentally fabricated by using 1-µm process technologies. The cell size and die size were 8 µm × 8 µm and 3 mm µ 3 mm, respectively. Access time was less than 100 ns.

A 1-/spl mu/m Mo-Poly 64-Kbit MOS RAM

This paper describes a 1-m 64-kbit MOS RAM using Mo-poly technology. New 1-/spl mu/ m double-gate technology using molybdenum and polysilicon (Mo-poly technology) is proposed. In this technology, molybdenum and polysilicon are used for word lines and storage capacitor electrodes in the memory cell, respectively. Therefore, the propagation delay in a word line becomes extremely small and memory cell size is reduced. New two step annealing was developed for stabilizing an Mo-gate MOS structure. Design is optimized for 1-/spl mu/ m Si-gate FET's in peripheral circuitry. A 1-/spl mu/ m Mo-poly 64-kbit MOS RAM was experimentally fabricated by using 1/spl mu/ m process technologies. The cell size and die size were 8 /spl mu/ m X 8 /spl mu/ m and 3 mm X 3 mm, respectively. Access time was less than 100 ns.

Proposed process modifications for dynamic bipolar memory to reduce emitter-base leakage current

One of the requirements of the dynamic bipolar memory cell is low junction leakage currents. Performance considerations, especially those of peripheral circuitry, may require that the memory is fabricated with the process commonly used in the fabrication of high-performance logic circuits, in which As emitters are used, and in which base surface concentrations are high. It is shown here that because of this, devices fabricated with this process have high emitter-to-base leakage current due to a presence of the tunneling component. It is further shown that this tunneling component can be reduced by simple modifications of the performance-oriented process. The experimental data presented here also show the observed changes in device parameters with various process modifications, which can be helpful in drawing a balance between a performance and leakage current requirements.

Proposed Process Modifications for Dynamic Bipolar Memory to Reduce Emitter-Base Leakage Current

One of the requirements of the dynamic bipolar memory cell is low junction leakage currents. Performance considerations, especially those of peripheral circuitry, may require that the memory is fabricated with the process commonly used in the fabrication of high-performance logic circuits, in which As emitters are used, and in which base surface concentrations are high. It is shown here that because of this, devices fabricated with this process have high emitter-to-base leakage current due to a presence of the tunneling component. It is further shown that this tunneling component can be reduced by simple modifications of the performance-oriented process. The experimental data presented here also show the observed changes in device parameters with various process modifications, which can be helpful in drawing a balance between performance and leakage current requirements.

A 256K-Bit Charge-Coupled Device Memory

This paper describes the design of an experimental 256K-bit serial-access memory using VLSI fabrication technology and low-power dynamic circuits. The memory array chip is implemented with a double polysilicon process and uses charge-coupled devices (CCDs) grouped in 64 blocks of 4K bits each. Operation is typically at a 300-ns-per-bit cycle for both read and write modes, with operating voltages of +8.5, +5.0, and -2.2 volts, and with 310 mW of power dissipation. All inputs and outputs, with the exception of a chip enable and two system clock lines, are TTL-level compatible. The unique design features and the organization of the 256K CCD chip are discussed; the array organization, the chip layout, the peripheral circuitry, and the buried-channel CCD device design are described; and test results obtained on experimental hardware are presented.

Monolithic 256-point programmable transversal filter

A 256-point programmable transversal filter has been integrated and assembled for use within a 16-pin d.i.l. package. The filter is realised in n-channel c.c.d./m.o.s. technology and incorporates novel operational amplifiers and other peripheral circuitry on-chip.

Causes and Mechanisms in Psychosomatic Phenomena

Abstract The bases for a presumed crisis in psychosomatic research are examined with special reference to the nature of evidence required to establish etiologic significance in the field of digestive diseases. Future research should exploit the rapid advances that have been developing in neurophysiology in order to identify the central and peripheral circuitry involved in psychosomatic mechanisms. In the experimental study of human subjects emphasis is needed on the interaction of a variety of potentially causative as well as protective factors. The modern sophisticated recording instruments may be of great value in documenting the perceptions of the investigator. The current trend away from descriptive research and human experimentation should be reversed. Medical research is basically a process of inquiry. The rigorous testing of hypotheses has its place, an important place, but enthusiasm for such should not be allowed to block the powerful inferences that may derive when a trained and talented observer records what he sees or experiences. Moreover, inability to replicate an event does not negate its authenticity. Descriptive evidence is usually called anecdotal and is thereby scorned. Darwin could provide a felicitous example here that many of the most revolutionary discoveries have resulted from astute observations and perceptive descriptions of relationships in nature. The work of Konrad Lorenz provides a more recent example.