Proposed Process Modifications for Dynamic Bipolar Memory to Reduce Emitter-Base Leakage Current

Abstract

One of the requirements of the dynamic bipolar memory cell is low junction leakage currents. Performance considerations, especially those of peripheral circuitry, may require that the memory is fabricated with the process commonly used in the fabrication of high-performance logic circuits, in which As emitters are used, and in which base surface concentrations are high. It is shown here that because of this, devices fabricated with this process have high emitter-to-base leakage current due to a presence of the tunneling component. It is further shown that this tunneling component can be reduced by simple modifications of the performance-oriented process. The experimental data presented here also show the observed changes in device parameters with various process modifications, which can be helpful in drawing a balance between performance and leakage current requirements.