Performance Penalty Research Articles

Neural Layered Decoding of 5G LDPC Codes

In this letter, we propose various low-complexity neural layered min-sum (NLMS) algorithms to improve the decoding performance of the fifth generation (5G) new radio (NR) low-density parity-check (LDPC) codes. Our proposals are based on the computationally-efficient normalized offset min-sum (NOMS) approach for the layered belief propagation (LBP). The main novelty of our proposals is a deep neural network (DNN) that implements the layered mode decoding and that additionally learns the normalization and the offset parameters of the NOMS scheme. The schemes that we propose use the DNN as well as adaptation and filtering for estimating the optimum values of these parameters. We show by simulation that our proposed decoders achieve a significant computational benefit compared to the standard (non-neural) LBP decoder without an appreciable performance penalty.

A high-speed and triple-node-upset recovery latch with heterogeneous interconnection

This paper presents an Interconnection heterogeneous and High-speed Triple-node-upset Recovery Latch (IHTRL). This latch utilizes homogeneous elements to construct a 4 × 4 array in four levels. The point is heterogeneous interconnection of each level. Compared with the traditional interconnection way, the proposed heterogeneous interconnection can block the propagation of TNU effectively. The IHTRL can effectively realize TNU recovery by the blocking ability of C-elements and heterogeneous interconnection. The IHTRL utilizes the high-speed path and clock-gating technique to reduce performance penalty and power consumption. Compared with TNU recovery latches LCTNURL and TNURL, the proposed IHTRL is the best in terms of delay, area overhead and PDP. Compared with TNU tolerant and recovery latches, the IHTRL achieves 81.96% reduction in delay on average, 85.91% reduction in PDP on average and 85.46% reduction in APDP on average, at the cost of 7.14% increase in power consumption and 13.21% increase in area overhead on average. Analysis shows that the IHTRL is insensitive to PVT variations.

Hydrotreated vegetable oil as enabler for high-efficient and ultra-low emission vehicles in the view of 2030 targets

Studies consider the influence of biofuels on the decarbonization of the transport system not negligible. The employment of fossil fuels with an even higher degree of renewable biofuel content, produced with a mature technology process, such as the Hydrotreated Vegetable Oils (HVO), are expected to increase. The research community expects valuable research results to exploit the HVO characteristics in ultra-low emission vehicles equipped with internal combustion engines. In this context, new findings in setting combustion control parameters through proper experimental design are carried out on a modern internal combustion engine architecture. An advanced injection system capable of precise close-coupled multiple injections per cycle was utilized. Steady-state engine operating conditions were selected for this experimental study. Combustion, efficiency, and engine-out emissions indicators with HVO fuel are compared with standard diesel. For assessing the difference in combustion stages, a second derivative method data analysis was performed. It is found that in comparison to diesel fuel, HVO significantly reduces regulated engine-out emissions at the same efficiency and EU 6c NOx emissions targets. To this aim, a specific set of engine control parameters were adopted. The PM decreased up to 10 %, corresponding to 0.18 g/kWh, while the CO2 reduced by about 7–8% in the range of 0.2–0.5 g/kWh. The decrease of the total PN ranges between 10 and 55%, depending on the control strategy and test point, and the particle distribution shifts towards smaller particle sizes. Outstanding improvements of the NOx-soot trade-off are verified, which in turn demonstrates the capability to operate the engine at post-EU6 NOx conditions without performance and comfort penalties. Engine-out CO and HC emission reductions are confirmed.

On the Competitiveness of Oblivious Routing: A Statistical View

Oblivious routing is a static algorithm for routing arbitrary user demands with the property that the competitive ratio, the proportion of the maximum congestion to the best possible congestion, is minimal. Oblivious routing turned out surprisingly efficient in this worst-case sense: in undirected graphs, we pay only a logarithmic performance penalty, and this penalty is usually smaller than 2 in directed graphs as well. However, compared to an optimal adaptive algorithm, which never causes congestion when subjected to a routable demand, oblivious routing surely has congestion. The open question is of how often is the network in a congested state. In this paper, we study two performance measures naturally arising in this context: the probability of congestion and the expected value of congestion. Our main result is the finding that, in certain directed graphs on n nodes, the probability of congestion approaches 1 in some undirected graphs, despite the competitive ratio being O(1).

An experimental investigation on the thermal augmentation of internal endwall in a two-pass duct using an array of delta-winglet vortex generator pair

The present study experimentally demonstrates a novel design for an internal endwall in a two-pass duct heat exchanger. An array of delta-winglet vortex generator pairs with different aspect ratio, angle of attack, configuration are mounted on the internal endwall in a U duct. Liquid crystal thermalgraphy and static pressure measurements are utilized in this study to evaluate the heat transfer, thermal-hydraulic performance, and pressure drop penalty. The Reynolds number is varied from 10,000 to 20,000. A comparison between the current novel design and traditional enhanced heat transfer turbulators in the open literature is also included. The results show that the endwall heat transfer is enhanced greatly as the longitudinal vortex generator array is located on the endwall. The variation of the attack angle has great influence on the endwall heat transfer, The endwall fitted with turbulators with an aspect ratio (length/height) of 2 and attack angle of 45-deg provides the highest thermal-hydraulic performance with a relatively low pressure drop penalty as long lasting longitudinal vortices might be induced at this attack angle and the heat transfer is observed to be enhanced at the downstream part of the endwall. In addition, for the temperature uniformity on the endwall, the local heat transfer at the upstream part still has the potential to be further improved for all studied cases. The optimal thermalhydraulic performance is increased by more than 24% compared with that on the endwall in the smooth U duct. This novel design presents a rather high overall thermal performance compared with the traditional design in the open literature.

Fault-tolerant neural network training framework based on client-server

In order to realize low power consumption and real-time inference, AIoT devices have been applied in many fields of deep learning in recent years. However, some manufacturing processes cause some soft errors on AIOT devices in inference. For a neural network accelerator with a large amount of computation, it may lead to a large amount of computing error and a huge loss of prediction accuracy, which is intolerable for precision-sensitive applications such as autonomous drones. However, conventional fault tolerance techniques such as triple modular redundancy can incur considerable power consumption and performance penalty. In this paper, a client-server collaborative fault-tolerant neural network training framework is proposed. In the training, an AIoT processor with soft errors is used as the client, and the server learns the on-site computing errors with the application data of AIoT processor. Several representative neural network models were selected in the experiment. Compared with the off-line training model, the model trained by this method increases the top5 accuracy of the neural network by an average of 2.8%.

Optical Phase Conjugation With Complex-Valued Deep Neural Network for WDM 64-QAM Coherent Optical Systems

We experimentally demonstrated a photoelectric nonlinear compensation scheme of optical phase conjugation (OPC) with complex-valued deep neural network (CVDNN) to mitigate fiber nonlinearity in wavelength division multiplexing (WDM) 64-QAM coherent optical transmission system. The factors to affect the performance of OPC and CVDNN are comprehensively considered. OPC in WDM system is experimentally optimized to alleviate the deployment requirements of strict symmetrical distributed power and chromatic dispersion. The performance penalty caused by the simplification of the OPC is further compensated by the CVDNN. The selections of the input neurons’ number and the optimization algorithm are also considered to design a simple two-hidden-layer-structure CVDNN. The proposed method is experimentally verified and evaluated in a 12.5-GBd 4-channel WDM 64-QAM 160-km standard single-mode fiber (SSMF) transmission system with channel spacing of 50-GHz. The experimental results show that the proposed nonlinear equalizer based on the OPC with CDVNN has a strong robustness to the input signal power and wavelength, which can not only improve the Q factor of the signal by 1.5-dB, but also greatly increase the total launched signal power.

Low Power Multiplication/Division Computing Unit forIOTApplications

Internet of things (IOT) makes limitation on power consumption for sensors and portable devices. Thus exact computation for multiplication and division processes are not allowed due to the huge amount of power consumption. To address these limitations, a low power multiplication/division computing unit is proposed. This approach is based on transforming the complex and power‐hungry multiplication and division operations to a simple addition and subtraction process. Then, the efficient piecewise uniform approximation logarithmic and antilogarithmic converters are utilized to complete the computation process. Synthesis of the proposed computing unit using 90 nm CMOS technology, 1.0 V supply voltage standard cell library with ‘typical corner’ operating condition, reveal that significant power dissipation savings are possible at no performance penalty, when compared with approximate computing approach. © 2021 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

RIN induced penalties in G.654.E and G.652.D based distributed Raman amplifiers for coherent transmission systems.

Relative intensity noise (RIN) induced penalties were experimentally measured in distributed Raman amplifiers (DRAs) for G.654.E and G.652.D fibres with forward, backward and bidirectional pumping configurations. The measured signal RIN using the G.654.E fibre was ∼3.5 dB and ∼2 dB lower than the G.652.D fibre with forward (FW) pump configuration for PM-QPSK and PM-8QAM signals, with single span transmission showing a Q-factor improvement of ∼3 dB and ∼2.5 dB for G.654.E over G.652.D fibres. The performance penalty in a long haul coherent system was evaluated for 28 GBaud PM-QPSK signals using a recirculation loop for backward and bidirectional distributed Raman amplifiers. Our experimental results demonstrate an additional transmission distance of more than 1000 km for G.654.E over its counterpart G.652.D assuming a HD-FEC limit of 8.5 dB.

Efficient machine learning on data science languages with parallel data summarization

Nowadays, data science analysts prefer “easy” high-level languages for machine learning computation like R and Python, but they present memory and speed limitations. Also, scalability is another issue when the data set size grows. On the other hand, acceleration of machine learning algorithms can be achieved with data summarization which has been a fundamental technique in data mining. With these motivations in mind, we present an efficient way to compute the statistical and machine learning models with parallel data summarization that can work with popular data science languages. Our summarization produces one or multiple summaries, accelerates a broader class of statistical and machine learning models, and requires a small amount of RAM. We present an algorithm that works in three phases and is capable to handle data sets bigger than the main memory. Our solution evaluates a vector–vector outer product with C++ code to escape the bottleneck of the high-level programming languages. We present an experimental evaluation section with a prototype in the R language where the summarization is programmed in C++. Our experiments prove that our solution can work on both data subsets and full data set without any performance penalty. Also, we compare our solution (R combined with C++) with other parallel big data systems: Spark (Spark-MLlib library), and a parallel DBMS (similar approach implemented with UDFs and SQL queries). We show our solution is simpler and mostly faster than Spark based on the storage of the data set, and it is much faster than a parallel DBMS regardless of the storage of the data set.

Optimization Model for Multiple Backup Resource Allocation With Workload-Dependent Failure Probability

This paper proposes a multiple backup resource allocation model with a workload-dependent failure probability to minimize the maximum expected unavailable time (MEUT) under a protection priority policy. The workload-dependent failure probability is a non-decreasing function which reveals the relationship between the workload and the failure probability. The proposed model adopts hot backup and cold backup strategies to provide protection. For protection of each function with multiple backup resources, it is required to adopt a suitable priority policy to determine the expected unavailable time. We analyze the superiority of the protection priority policy for multiple backup resources in the proposed model; we provide the theorems that clarify the influence of policies on MEUT. We formulate the optimization problem as a mixed integer linear programming (MILP) problem. We provide a lower bound of the optimal objective value in the proposed model. We prove that the decision version of the multiple resource allocation problem in the proposed model is NP-complete. A heuristic algorithm inspired by the water-filling algorithm is developed with providing an upper bound of the expected unavailable time obtained by the algorithm. The numerical results show that the proposed model reduces MEUT compared to baselines. The priority policy adopted in the proposed model suppresses MEUT compared with other priority policies. The developed heuristic algorithm is approximately 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> times faster than the MILP approach with 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> performance penalty on MEUT.

A high-performance VLSI array reconfiguration scheme based on network flow under row and column rerouting

The reconfiguration algorithms have been extensively investigated to ensure the reliability and stability for the processor arrays with faults. It is important to reduce the power consumption, capacitance and communication costs in the processors by reducing the interconnection length of the VLSI array. This paper discusses the reconfiguration problem of the high-performance VLSI processor array under the row and column rerouting constraints. A novel method, making use the idea of network flow, is proposed in this paper. Firstly, a network flow model of the VLSI processor array is constructed, such that the high-performance VLSI target array can be obtained by utilizing the minimal cost flow algorithm. Secondly, we propose a new strategy for bottleneck row selection in the logical array using the minimum cut technique, which can find a more suitable bottleneck row. Finally, we conducted reliable experiments to clearly reveal the efficiency of the new rerouting scheme and algorithm in reducing the number of long interconnects. The experimental results show that, for a host array with size of 256×256, the number of long interconnects in the subarray can be reduced by up to 79.22% and 55.88% without performance penalty for random faults with density of 1% and 25% respectively, when compared with state-of-the-art. In addition, the proposed scheme improves existing algorithm in terms of subarray size. On a 256×256 host array with 25% faulty density, the average improvement in subarray size is up to 3.77% compared with state-of-the-art.

Getting to the point: index sets and parallelism-preserving autodiff for pointful array programming

We present a novel programming language design that attempts to combine the clarity and safety of high-level functional languages with the efficiency and parallelism of low-level numerical languages. We treat arrays as eagerly-memoized functions on typed index sets, allowing abstract function manipulations, such as currying, to work on arrays. In contrast to composing primitive bulk-array operations, we argue for an explicit nested indexing style that mirrors application of functions to arguments. We also introduce a fine-grained typed effects system which affords concise and automatically-parallelized in-place updates. Specifically, an associative accumulation effect allows reverse-mode automatic differentiation of in-place updates in a way that preserves parallelism. Empirically, we benchmark against the Futhark array programming language, and demonstrate that aggressive inlining and type-driven compilation allows array programs to be written in an expressive, "pointful" style with little performance penalty.

Side-Channel Protections for Picnic Signatures

We study masking countermeasures for side-channel attacks against signature schemes constructed from the MPC-in-the-head paradigm, specifically when the MPC protocol uses preprocessing. This class of signature schemes includes Picnic, an alternate candidate in the third round of the NIST post-quantum standardization project. The only previously known approach to masking MPC-in-the-head signatures suffers from interoperability issues and increased signature sizes. Further, we present a new attack to demonstrate that known countermeasures are not sufficient when the MPC protocol uses a preprocessing phase, as in Picnic3.We overcome these challenges by showing how to mask the underlying zero-knowledge proof system due to Katz–Kolesnikov–Wang (CCS 2018) for any masking order, and by formally proving that our approach meets the standard security notions of non-interference for masking countermeasures. As a case study, we apply our masking technique to Picnic. We then implement different masked versions of Picnic signing providing first order protection for the ARM Cortex M4 platform, and quantify the overhead of these different masking approaches. We carefully analyze the side-channel risk of hashing operations, and give optimizations that reduce the CPU cost of protecting hashing in Picnic by a factor of five. The performance penalties of the masking countermeasures ranged from 1.8 to 5.5, depending on the degree of masking applied to hash function invocations.

Aerodynamic interaction between propellers of a distributed-propulsion system in forward flight

This article describes an experimental investigation of the aerodynamic interaction that occurs between distributed propellers in forward flight. To this end, three propellers were installed in close proximity in a wind tunnel, and the changes in their performance, flow-field characteristics, and noise production were quantified using internal force sensors, total-pressure probes, particle-image velocimetry (PIV), and microphones recessed in the wind-tunnel wall. At the thrust setting corresponding to maximum efficiency, the efficiency of the middle propeller is found to drop by 1.5% due to the interaction with the adjacent propellers, for a tip clearance equal to 4% of the propeller radius. For a given blade-pitch angle, this performance penalty increases with angle of attack, decreasing thrust setting, or a more upstream propeller position, while being insensitive to the rotation direction and relative blade phase angle. Furthermore, the velocities induced by the adjacent propeller slipstreams lead to local loading variations on the propeller disk of 5% – 10% of the average disk loading. Exploratory noise measurements show that the interaction leads to different tonal noise waveforms of the system when compared to the superposition of isolated propellers. Moreover, the results confirm that an active control of the relative blade phase angles between propellers can effectively modify the directivity pattern of the system.

Time-domain uplink synchronization method for a spectral efficient OFDMA-based PON

The feasibility of a time-domain technique, proposed for uplink synchronization of the bandwidth scalable orthogonal frequency division multiple access passive optical network (BS-OFDMA PON), is experimentally demonstrated. The results show that a delay variation of less than 50% of the cyclic prefix is tolerable, relaxing the thin time synchronization required in the uplink of the evaluated architecture. Moreover, we enhance the spectral efficiency of the BS-OFDMA PON by reducing the guard band ( B g ) between the optical carrier and the signal bandwidth, as well as by eliminating the frequency gap ( Δ f G ) between the optical network units. The downlink results demonstrate that Δ f G can be eliminated with negligible performance penalties, and B g can be reduced to almost half the signal bandwidth. Error-free transmissions were achieved after uplink propagation over 45 km of single-mode fibers with received power of ≈ − 16.8 d B m and B g = 450 M H z , with a signal bandwidth of 1 GHz.

Numerical method to predict ice accretion shapes and performance penalties for rotating vertical axis wind turbines under icing conditions

This paper proposes a numerical method to predict the ice accretion shapes and aerodynamic performance of rotating vertical axis wind turbine (VAWTs) under icing conditions. A multiple reference frame (MRF) and sliding mesh technique (SMT) are combined to efficiently reflect the unsteady icing effects on rotating wind turbines. The SMT calculates the flow field considering the rotational and unsteady effects of the VAWTs. The MRF can efficiently clarify the rotational effects of the droplet field and ice accretion. Using the MRF technique, a series of icing simulations is implemented in which the ice shapes are updated at azimuth angle intervals of 36°. Using the proposed method, ice shapes in agreement with those obtained in icing wind tunnel tests can be obtained. Moreover, ice that is evenly distributed over the blade surface under glaze ice conditions can be examined instead of only the forms concentrated on the leading-edge, such as ice horns. The overall output power of an ice-covered VAWT is noted to be significantly reduced. Massive flow separation is induced owing to the increased airfoil thickness at azimuthal angles between 0° and 180°. Nevertheless, the performance of the thickened airfoil is enhanced owing to the delayed flow separation via dynamic stall in azimuthal angles between 180° and 270°.

Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache

Many emerging non-volatile memories are compatible with CMOS logic, potentially enabling their integration into a CPU’s die. This article investigates such monolithically integrated CPU–main memory chips. We exploit non-volatile memories employing 3D crosspoint subarrays, such as resistive RAM (ReRAM), and integrate them over the CPU’s last-level cache (LLC). The regular structure of cache arrays enables co-design of the LLC and ReRAM main memory for area efficiency. We also develop a streamlined LLC/main memory interface that employs a single shared internal interconnect for both the cache and main memory arrays, and uses a unified controller to service both LLC and main memory requests. We apply our monolithic design ideas to a many-core CPU by integrating 3D ReRAM over each core’s LLC slice. We find that co-design of the LLC and ReRAM saves 27% of the total LLC–main memory area at the expense of slight increases in delay and energy. The streamlined LLC/main memory interface saves an additional 12% in area. Our simulation results show monolithic integration of CPU and main memory improves performance by 5.3× and 1.7× over HBM2 DRAM for several graph and streaming kernels, respectively. It also reduces the memory system’s energy by 6.0× and 1.7×, respectively. Moreover, we show that the area savings of co-design permits the CPU to have 23% more cores and main memory, and that streamlining the LLC/main memory interface incurs a small 4% performance penalty.

Passage shock wave/boundary layer interaction control for transonic compressors using bumps

Flow separation due to shock wave/boundary layer interaction is dominated in blade passage with supersonic relative incoming flow, which always accompanies aerodynamic performance penalties. A loss reduction method for smearing the passage shock foot via Shock Control Bump (SCB) located on transonic compressor rotor blade suction side is implemented to shrink the region of boundary layer separation. The curved windward section of SCB with constant adverse pressure gradient is constructed ahead of passage shock-impingement point at design rotor speed of Rotor 37 to get the improved model. Numerical investigations on both two models have been conducted employing Reynolds-Averaged Navier-Stokes (RANS) method to reveal flow physics of SCB. Comparisons and analyses on simulation results have also been carried out, showing that passage shock foot of baseline is replaced with a family of compression waves and a weaker shock foot for moderate adverse pressure gradient as well as suppression of boundary layer separations and secondary flow of low-momentum fluid within boundary layer. It is found that adiabatic efficiency and total pressure ratio of improved blade exceeds those of baseline at 95%-100% design rotor speed, and then slightly worsens with decrease of rotatory speed till both equal below 60% rated speed. The investigated conclusion implies a potential promise for future practical applications of SCB in both transonic and supersonic compressors.

Numerical Investigation on the Influences of Boundary Layer Ingestion on Tip Leakage Flow Structures and Losses in a Transonic Axial-Flow Fan

Abstract In a boundary layer ingesting (BLI) propulsion system, the fan is continuously exposed to inflow distortions. The distorted inflows lead to nonuniform loss distributions along the radial and circumferential directions. Since the rotor tip suffers from higher intensive distortion, the local loss increment is a major contributor to the BLI fan performance penalty. To explore the effects of distorted inflows on tip leakage flow evolutions and associated mechanisms for increased loss in a BLI fan, three-dimensional full-annulus unsteady simulations are conducted. Results show that about 54% of total additional losses due to distortion are formed in the tip region and more than 80% of tip region entropy generation is related to the tip leakage flow. The intensities of leakage vortex–shock interactions vary at different annulus locations. When the rotor moves into the distorted region, the vortex–shock interaction is weaker than the undistorted locations due to attenuated leakage flow. At the locations where the rotor is moving out from the distorted region, the vortex–shock interaction is notably enhanced because the front part of the blade tip airfoil suffers a higher load, resulting in a rapid vortex core expansion and eventually vortex breakdown. The increase of flow blockage in the front section of blade tip passages at local circumferential positions leads to a corresponding rise of flow loss. The findings in this study highlight the impacts of tip leakage flow on aerodynamic loss of fan working under BLI inflow distortion and provide improved understandings of loss mechanisms in a BLI fan.