A high-speed and triple-node-upset recovery latch with heterogeneous interconnection

Abstract

This paper presents an Interconnection heterogeneous and High-speed Triple-node-upset Recovery Latch (IHTRL). This latch utilizes homogeneous elements to construct a 4 × 4 array in four levels. The point is heterogeneous interconnection of each level. Compared with the traditional interconnection way, the proposed heterogeneous interconnection can block the propagation of TNU effectively. The IHTRL can effectively realize TNU recovery by the blocking ability of C-elements and heterogeneous interconnection. The IHTRL utilizes the high-speed path and clock-gating technique to reduce performance penalty and power consumption. Compared with TNU recovery latches LCTNURL and TNURL, the proposed IHTRL is the best in terms of delay, area overhead and PDP. Compared with TNU tolerant and recovery latches, the IHTRL achieves 81.96% reduction in delay on average, 85.91% reduction in PDP on average and 85.46% reduction in APDP on average, at the cost of 7.14% increase in power consumption and 13.21% increase in area overhead on average. Analysis shows that the IHTRL is insensitive to PVT variations.