Performance Of ZnO Thin-film Transistors Research Articles

High-Performance Thin-Film Transistors with ZnO:H/ZnO Double Active Layers Fabricated at Room Temperature.

H doping can enhance the performance of ZnO thin-film transistors (TFTs) to a certain extent, and the design of double active layers is an effective way to further improve a device's performance. However, there are few studies on the combination of these two strategies. We fabricated TFTs with ZnO:H (4 nm)/ZnO (20 nm) double active layers by magnetron sputtering at room temperature, and studied the effect of the hydrogen flow ratio on the devices' performance. ZnO:H/ZnO-TFT has the best overall performance when H2/(Ar + H2) = 0.13% with a mobility of 12.10 cm2/Vs, an on/off current ratio of 2.32 × 107, a subthreshold swing of 0.67 V/Dec, and a threshold voltage of 1.68 V, which is significantly better than the performance of single active layer ZnO:H-TFTs. This exhibits that the transport mechanism of carriers in double active layer devices is more complicated. On one hand, increasing the hydrogen flow ratio can more effectively suppress the oxygen-related defect states, thus reducing the carrier scattering and increasing the carrier concentration. On the other hand, the energy band analysis shows that electrons accumulate at the interface of the ZnO layer close to the ZnO:H layer, providing an additional path for carrier transport. Our research exhibits that the combination of a simple hydrogen doping process and double active layer construction can achieve the fabrication of high-performance ZnO-based TFTs, and that the whole room temperature process also provides important reference value for the subsequent development of flexible devices.

The impact of multi-layered dielectrics on the electrical performance of ZnO thin-film transistors

The electrical performance of ZnO thin film transistors (TFTs) fabricated on three different dielectric layers is investigated using an inverted staggered bottom gate thin film transistor structure. This work demonstrated the potential of integrating high-k dielectrics in ZnO TFTs in a dielectric multi-layered stack using SiO2 as the support layer for all the hero-dielectrics layers. In order to achieve this, ZnO thin film semiconducting layers were deposited at room temperature by radio frequency (RF) sputtering method and with no post deposition heat treatment, making them suitable candidates for low cost large area electronics on low temperature substrates (such as plastics). The dielectric films investigated were aluminium nitride (AlN), silicon nitride (SiN) and silicon dioxide (SiO2). The effective mobility of SiN devices was about half that observed in AlN devices. However, the dielectric layers exhibited hysteresis of approximately 0 V, 2 V and 7 V for the SiO2, AlN and SiN respectively. In addition, SiO2 TFTs have lowest threshold voltage (VT) and turn-on voltage (Von). The capacitance-voltage measurement for these device show that the flatband and threshold voltage of SiN and AlN MOS capacitors shifted towards more negative voltages instead when compared with the single layer SiO2 devices.

Rational design of hydrogen and nitrogen co-doped ZnO for high performance thin-film transistors

This work investigates the effect of nitrogen and hydrogen (N/H) co-doping on the performance of ZnO thin-film transistors (TFTs). Optimum N/H co-doped ZnO TFTs showed high field-effect mobility (25.5 cm2 Vs−1) and Ion/Ioff (107) and low sub-threshold slope (0.25 V/dec.) and threshold voltage (1.2 V). X-ray photo-electron spectroscopy (XPS) and low-frequency noise analysis suggest that the observed improved electrical performance may be attributed to the reduction of the defect concentration and the average interface trap density due to the occupation of the NO–H complex on the oxygen vacancy and Zn interstitials. Moreover, density functional theory calculation and XPS band structure results demonstrate that the N/H co-doped ZnO film slightly changed the valence band maximum energy offset, indicating that the N/H co-doping controlled the carrier concentration of the ZnO film due to the formation of neutral complex N–H states. The enhanced electrical performance of the N/H co-doped ZnO TFT shows significant potential for the use of low-cost thin film electronic applications.

Application of Taguchi arrays using DOE for optimizing processing and understanding sputtered coated ZnO TFTs

This study applies the Taguchi orthogonal array (OA) to improve and optimize the performance of ZnO thin-film transistors (TFT). Radiofrequency (RF) sputtering method was used to deposit the active layer of TFTs. The annealing temperature, environmental conditions, sputter rate, and thin-film thickness were the parameters whose impact on output parameters like mobility was analyzed in the process optimization using design of experiment (DOE). The ZnO TFTs show state-of-the-art performance features, including high saturation mobility (0.83c), high Ion/Ioff ratio (104). The optimal configuration was found to be high annealing temperature 450 °C under N2 atmosphere, low sputter rate. This paper presents a method that can empower the fast optimization of metal oxide TFTs for future developments in the manufacturing process. If a full factorial design had been implemented, 64 tests would have been necessary, however in this work, we have reduced the number of tests to 9 only using Taguchi method.

Effect of photochemical hydrogen doping on the electrical properties of ZnO thin-film transistors

We examined the effect of photochemical hydrogen doping on the performance of ZnO thin-film transistors (TFTs). H atoms were doped into the ZnO active layers (ZnO:H) by irradiation at two different ultraviolet (UV) wavelengths, 185 and 254 nm, for 0, 2, 4, and 6 h. Then, the ZnO surface before and after H doping was analyzed using X-ray photoelectron spectroscopy and X-ray diffraction. The ZnO surface exhibited metal–OH bonding states and the oxygen vacancy increased with the UV irradiation time. In addition, the surface roughness of the ZnO thin film decreased from 1.634 to 1.385 nm because of the increasing hydrophilicity as the oxygen vacancy increased, reducing the trap sites and electron scattering at the channel/insulator interface, thus improving the TFT performance. Among the samples, the ZnO:H TFTs with 6 h of UV irradiation time exhibited the best performance, the saturation mobility increased from 1.56 to 14.2 cm2/Vs, the on/off ratio increased from 105 to 1.1 × 106, and the threshold voltage decreased from 5.42 to 2 V compared to the ZnO TFTs with no UV irradiation.

Improving the Performance of ZnO Thin-Film Transistors with ZnON Source/Drain Contacts

Motivation to study the ZnO channel for thin-film transistors (TFTs) is strong in light of its decent high mobility and large bandgap, enabling simultaneous coexistence of high on current and low off-state leakage. Nevertheless, the improvement in device performance for ZnO TFTs has not been fully exercised and even the field-effect mobility ( $\mu _{\text {FE}}$ ) is degraded with downscaling the channel length owing to considerable series source/drain (S/D) resistance ( ${R}_{\text {SD}}$ ). In this paper, we show that inserting a thin contact layer of ZnON between the ZnO channel and Al S/D effectively suppresses the formation of interfacial layer of AlO x and thereby reduces ${R} _{\text {SD}}$ dramatically. This is evidenced by a significant reduction in ${R} _{\text {SD}}$ from 30.1 to 14.4 $\text{k}\Omega \cdot \mu \text{m}$ measured on 0.5- $\mu \text{m}$ ZnO TFTs with a ZnON contact layer or not, leading to an improvement in $\mu _{\text {FE}}$ from 18.2 to 29.6 cm $^{2}/\text {V}\cdot \text {s}$ .

Correlation between nano-scale microstructural behavior and the performance of ZnO thin-film transistors.

Binary ZnO active layers possessing a polycrystalline structure were deposited with various argon/oxygen flow ratios at 250 degrees C via sputtering. Then ZnO thin-film-transistors (TFTs) were fabricated without additional thermal treatments. As the oxygen content increased during the deposition, the preferred orientation along the (0002) was weakened and the rotation of the grains increased, and furthermore, less conducting films were observed. On the other hand, the reduced oxygen flow rate induced the formation of amorphous-like transition layers during the initial growth due to a high growth rate and high energetic bombardment of the adatoms. As a result, the amorphous phases at the gate dielectric/channel interface were responsible for the formation of a hump shape in the subthreshold region of the TFT transfer curve. In addition, the relationship between the crystal properties and the shift in the threshold voltage was experimentally confirmed by a hysteresis test.

Self-assembled nanocrystalline ZnO thin film transistor performance optimization for high speed applications

ZnO nanocrystals grown at relatively low temperatures using various vacuum deposition techniques can yield semiconducting thin films of self-assembled nanocolumns 20-50 nm in diameter. Such films are suitable for the fabrication of high speed and transparent thin film transistors (TFTs). Unlike amorphous TFTs, the performance of ZnO transistors depends both on the crystal quality of nanocrystals and the electrical properties of boundary layers between them. We investigated the use of radio frequency sputtering, atomic layer deposition, and pulsed laser deposition techniques to fabricate self-assembled nanocrystalline thin films and determined the influence of deposition conditions on the performance of transistors. Device design and fabrication parameters were also optimized to demonstrate TFTs with high current density and high speed performance comparable to single crystalline-based transistors.

Chemical composition and temperature dependent performance of ZnO-thin film transistors deposited by pulsed and continuous spray pyrolysis

Zinc oxide thin film transistors (TFTs) deposited by continuous and pulsed spray pyrolysis were investigated to analyze process kinetics which make reduction of process temperature possible. Thus, fluid mechanics, chemical composition, electrical performance, and deposition and annealing temperature were systematically analyzed. It was found that ZnO layers continuously deposited at 360 °C contained zinc oxynitrides, CO3, and hydro carbonate groups from pyrolysis of basic zinc acetate. Statistically, every second wurtzite ZnO unit cell contained an impurity atom. The purity and performance of the ZnO-TFTs increased systematically with increasing deposition temperature due to an improved oxidation processes. At 500 °C the zinc to oxygen ratio exceeded a high value of 0.96. Additionally, the ZnO film was not found to be in a stabilized state after deposition even at high temperatures. Introducing additional subsequent annealing steps stabilizes the film and allows the reduction of the overall thermal stress to the substrate. Further improvement of device characteristics was obtained by pulsed deposition which allowed a more effective transport of the by-products and oxygen. A significant reduction of the deposition temperature by 140 °C was achieved compared to the same performance as in continuous deposition mode. The trap density close to the Fermi energy could be reduced by a factor of two to 4 × 1017 eV−1 cm−3 due to the optimized combustion process on the surface. The optimization of the deposition processes made the fabrication of TFTs with excellent performance possible. The mobility was high and exceeded 12 cm2/V s, the subthreshold slope was 0.3 V dec−1, and an on-set close to the ideal value of 0 V was achieved.

Enhancement of ZnO thin film transistor performance by high-dose proton irradiation

Abstract The object of this study was to improve the performance of ZnO thin film transistors (TFTs) by exposing them to high-dose proton irradiation. A rapid thermal annealing (RTA) process was necessary to improve the interface characteristics between the source–drain electrodes and the channel layer for the high performance of ZnO-TFTs. However, this affected the resistivity of the ZnO channel layer; it was dramatically decreased during the RTA process. As a result, the RTA-treated ZnO-TFTs did not show the proper off-state characteristics. In order to control the electrical properties of the channel layer, we exposed the RTA-treated ZnO-TFTs to 6.1 MeV of proton irradiation beam energy at fluences from 6.7 × 1012 cm−2 to 6.5 × 1014 protons-cm−2. The resulting resistivity of the ZnO thin film increased after the high-dose proton irradiation. In addition, we studied the structural and electrical properties and the variations in the native defects of ZnO thin films. The field effective mobility of ZnO-TFTs increased from 1.65 to 4.12 cm2/V s after both the RTA and the high-dose proton irradiation. We obtained an enhancement of ZnO-TFT performance using high-dose proton irradiation.

Understanding the role of the insulator in the performance of ZnO TFTs

The performance and stability of ZnO thin film transistors (TFTs) with three different insulators are examined. It is found that the on-state performance is significantly enhanced with AlN as gate insulator in comparison to SiO 2 or SiN. This behaviour is consistent with the excellent lattice match of AlN with ZnO which results in reduction of subthreshold slope. Despite enhanced on-state performance the shift in threshold voltage under gate bias stress however appears unmitigated. Stability in ZnO is primarily due to trapping within the bulk of the semiconductor and/or close to the interface.

The Effect of Gate-Bias Stress and Temperature on the Performance of ZnO Thin-Film Transistors

The stability of ZnO thin-film transistors is investigated by using gate-bias stress. It is found that the application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. It is postulated that this device instability is a consequence of charge trapping at or near the channel/insulator interface. In addition, there is a degradation of subthreshold behavior and channel mobility, which is suggested to result from the defect-state creation within the ZnO layer. The effect of elevated temperature stress shows a predominance of interface-state creation in comparison to trapping under gate-bias stress. Device instability appears to be a consequence of the charging and discharging of preexisting trap states at the interface and in the channel region of the devices. All stressed devices recover their original characteristics after a short period at room temperature without the need for any thermal or bias annealing.

Modeling and simulation of polycrystalline ZnO thin-film transistors

Thin-film transistors (TFTs) made of transparent channel semiconductors such as ZnO are of great technological importance because their insensitivity to visible light makes device structures simple. In fact, there have been several demonstrations of ZnO TFTs achieving reasonably good field effect mobilities of 1–10 cm2/V s, but the overall performance of ZnO TFTs has not been satisfactory, probably due to the presence of dense grain boundaries. We modeled grain boundaries in ZnO TFTs and performed simulation of a ZnO TFT by using a two-dimensional device simulator in order to determine the grain boundary effects on device performance. Polycrystalline ZnO TFT modeling was started by considering a single grain boundary in the middle of the TFT channel, formulated with a Gaussian defect distribution localized in the grain boundary. A double Schottky barrier was formed in the grain boundary, and its barrier height was analyzed as a function of defect density and gate bias. The simulation was extended to TFTs with many grain boundaries to quantitatively analyze the potential profiles that developed along the channel. One of the main differences between a polycrystalline ZnO TFT and a polycrystalline Si TFT is that the much smaller nanoscaled grains in a polycrystalline ZnO TFT induces a strong overlap of the double Schottky barriers with a higher activation energy in the crystallite and a lower barrier potential in the grain boundary at subthreshold or off-state region of its transfer characteristics. Through the simulation, we were able to estimate the density of total trap states localized in the grain boundaries for polycrystalline ZnO TFT by determining the apparent mobility and grain size in the device.