Transistor Performance Research Articles

Analytical modeling of architecture dependent atypical scaling trends in metal–Hf0.5Zr0.5O2–metal-SiO2–Si negative capacitance transistors

In order to better understand the possible improvement through the incorporation of a ferroelectric (FE) layer in the gate stack of the nanoscale transistor, this work develops analytical expressions to assess the scalability of cylindrical (CYL) nanowire and planar double gate (DG) metal–FE–metal–insulator–semiconductor (MFMIS) negative capacitance (NC) transistors. While predicting a sub-60 mV dec−1 subthreshold swing and a negative drain induced barrier lowering (DIBL), the results indicate that at lower FE thickness, the performance of the NC field effect transistor (NCFET) is primarily governed by the electrostatic integrity of the baseline transistor, i.e. the CYL architecture outperforms planar DG NCFET. However, for relatively thicker T FE, the performance of an MFMIS NCFET is strongly governed by the FE coupling, which indicates the comparable performance of DG and CYL MFMIS NCFETs. The formalism, while predicting atypical trends, showcases a pragmatic design criterion for achieving a sub-60 mV dec−1 subthreshold swing and DIBL-free characteristics in MFMIS NC transistors.

Controlled orientation and microstructure of p-type SnO thin film transistors with high-k dielectric for improved performance

Despite its relatively high hole mobility, the electrical performance of p-type SnO thin-film transistors (TFTs) lags behind that of n-type oxide TFTs. In this study, we present an approach to enhance the performance of p-type SnO TFTs by utilizing an atomic-layer-deposited SnO/high-k structure, with crystalline HfO2 (c-HfO2) serving as a high-k dielectric. However, the grain boundaries on the c-HfO2 surface influenced the microstructure and orientation of the SnO layer, resulting in a random orientation and surface roughening. To address this issue, we modified the c-HfO2 surface with an amorphous ultrathin Al2O3 layer to eliminate the grain boundaries on the deposition surface. This enabled the alignment of the (00l) SnO planes parallel to the substrate surface and provided a smooth surface. Moreover, the introduction of ultrathin Al2O3 into SnO/high-k stacks substantially improved the electrical performance of p-type SnO TFTs. Our findings highlight the potential of integrating van der Waals semiconductors with high-k dielectrics, facilitating opportunities for advanced device applications.

Experimental study of MISHEMT from 450 K down to 200 K for analog applications

This work presents an experimental analysis of Metal-Insulator-Semiconductor High Electron Mobility transistor (MISHEMT) operating in a temperature range from 450 K down to 200 K, focusing on analog applications. The drain current and consequently the saturation transconductance (gmsat) showed to be slightly dependent on gate length. The output conductance (gD) presents a higher dependence with gate length than gmsat for the whole temperature range due to the influence of MOS conduction that is strongly affected by short channel effect. There is also a kink in the behavior of these parameters at 350 K, most likely due to the competition of temperature effects on different conduction mechanisms. The transistors showed a good performance in terms of analog application, where the intrinsic voltage gain (AV) increases from 38 dB (at 200 K) to 43 dB (at 450 K) for 800 nm gate length while the unity gain frequency (fT) decreases from 1.8 GHz (at 200 K) to 800 MHz (at 450 K) for a gate length of 400 nm, which makes MISHEMT a good candidate for analog applications.

Assessment of the Testing Methods for Evaluating the Performance of Organic Electrochemical Transistors

Assessment of the Testing Methods for Evaluating the Performance of Organic Electrochemical Transistors

Utilizing Dip-Coating to Fabricate Gate Dielectric and Semiconductor for Thin-Film Transistors

The potential applications of advanced electronic materials in large-area, printable, and flexible electronics have generated significant interest. However, creating high-performance, low-voltage thin-film transistors (TFTs) for these applications remains difficult due to a lack of advanced gate dielectric and semiconductor materials that meet both ease-of-fabrication requirements and high electrical performance. In this study, we present high-performance gate dielectric thin-films, which were fabricated using a facile solution-based technique, and then employed to realize low operating voltage organic and metal oxide semiconductor-based thin-film transistors. The high-k oxide gate dielectrics were produced via a simple dip-coating method, resulting in the formation of thin-oxide layers. These novel oxide gate dielectrics demonstrated exceptional dielectric properties, with large capacitances (up to 430 nF/ cm2), low-level leakage current densities (< 3 × 10-8A/cm2 at 4 V), featureless morphology (rms roughness < 0.36 nm), and high transparency (> 85%). Consequently, these dip-coated gate dielectrics can be incorporated into thin-film transistors, utilizing pentacene as p-type organic semiconductors. Furthermore, by employing dip-coating, indium oxide and indium-gallium-zinc oxide can be utilized as n-type inorganic semiconductors, allowing for the fabrication of low-voltage operation and high-performance inorganic TFTs. The resulting TFTs functioned at ultralow voltages (< ± 2 V) and achieved high transistor performance (hole mobility: 0.28 cm2V-1·s-1, electron mobility: ~2.0 cm2V-1·s-1 and on/off current ratio >105).

Well-Balanced Ambipolar Charge Transport of Diketopyrrolepyrrole-Based Copolymers: Organic Field-Effect Transistors and High-Voltage Logic Applications.

A poly (3,6-bis(thiophen-2-yl)-2,5-bis(2-decyltetradecyl)-2,5-dihydropyrrolo[3,4-c]pyrrole-1,4-dione-co-(2,3-bis(phenyl)acrylonitrile)) (PDPADPP) copolymer, composed of diketopyrrolopyrrole (DPP) and a cyano (nitrile) group with a vinylene spacer linking two benzene rings, is synthesized via a palladium-catalyzed Suzuki coupling reaction. The electrical performance of PDPADPP in organic field-effect transistors (OFETs) and circuits is investigated. The OFETs based on PDPADPP exhibit typical ambipolar transport characteristics, with the as-cast OFETs demonstrating low field-effect hole and electron mobility values of 0.016 and 0.004cm2 V-1 s-1 , respectively. However, after thermal annealing at 240°C, the OFETs exhibit improved transport characteristics with highly balanced ambipolar transport, showing average hole and electron mobility values of 0.065 and 0.116cm2 V-1 s-1 , respectively. To verify the application of the PDPADPP OFETs in high-voltage logic circuits, compact modeling using the industry-standard small-signal Berkeley short-channel IGFET model (BSIM) is performed, and the logic application characteristics are evaluated. The circuit simulation results demonstrate excellent logic application performance of the PDPADPP-based ambipolar transistor and illustrate that the device annealed at 240°C exhibits ideal circuit characteristics.

Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications

This work presents an experimental evaluation of n-type, gate-all-around (GAA), vertically stacked nanosheet field effect transistors (NSFETs) operating in a temperature (T) range from 473 K down to 173 K and focusing on their use for analog applications. Devices with gate lengths (Lgate) of 28 nm to 200 nm were analyzed. Besides exhibiting a slight short channel effect, the shorter transistors show a good performance in terms of analog application, presenting at 173 K an intrinsic voltage gain (AV) of 30 dB and unit gain frequency (fT) of 185 GHz. This is also seen in two figures of merit that characterize the transistor performance for analog circuit design: the transistor efficiency (gm/IDS) and the gain frequency product (AV*fT). The optimum region of operation was demonstrated to be at strong inversion by the trade-off between gm/IDS and fT, where in this region Lgate = 28 nm presents a gain frequency product of ∼ 5,5THz at T = 173 K. At lower temperature, as expected, it is confirmed that the carrier mobility and the subthreshold swing (SS) improve while the threshold voltage (VT) increases.

Theoretical Study of Self-Heating-Induced Thermal Stress Effects on Quantum Transport in p-Type Ultrathin Body-FinFET by Multiphysics Simulation

Self-heating of the device will intensify the thermo-mechanical effects, leading to an increase in thermal stress. Currently, most of the research focuses on strain engineering of the device by intentionally introducing mechanical stress. However, how thermal stress affects the performance of nanoscale transistors remains unclear. Thus, in this manuscript, a comprehensive coupled Multiphysics simulation is performed to investigate the self-heating induced thermal stress effects on quantum transport in the p-type ultrathin body (UTB)-FinFET. The quantum transport equation with consideration of thermal stress effects by the strain term in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{k}\cdot \textit{p}$</tex-math> </inline-formula> Hamiltonian, heat conduction equation, and equilibrium equations of solid mechanics are solved self-consistently. Then, the impacts of self-heating-induced thermal stress on hole effective mass, hole average velocity, and current density of the FinFETs with different crystal orientation configurations and channel lengths are compared and analyzed. The simulation results show that thermal stress can decrease or increase the ON-state current depending on the crystal orientation configuration. Further analysis of the band structure obtained from the Hamiltonian shows that thermal stress can change the material properties such as the hole effective mass of the top subband, thus leading to the variations of device characteristics.

The Effect of Alkyl Chain Length in Organic Semiconductor and Surface Polarity of Polymer Dielectrics in Organic Thin-Film Transistors (OTFTs).

The interface between dielectric and organic semiconductor is critically important in determining organic thin-film transistor (OTFT) performance. Surface polarity of the dielectric layer can hinder charge transport characteristics, which has restricted utilization of polymeric dielectric materials containing polar functional groups. Herein, the electrical characteristics of OTFTs are analyzed depending on the alkyl chain length of organic semiconductors and surface polarity of polymer dielectrics. High-performance dibenzothiopheno[6,5-b:6',5'-f]thieno[3,2-b]thiophene (DBTTT) and newly synthesized its alkylated derivatives (C6-DBTTT and C10-DBTTT) are utilized as organic semiconductors. As dielectric layers, non-polar poly(1,3,5-trimethyl-1,3,5-trivinylcyclitrisiloxane) (pV3D3) and poly(2-cyanoethyl acrylate-co-diethylene glycol divinyl ether) [p(CEA-co-DEGDVE)] with polar cyanide functionality are utilized. The fabricated OTFTs with pV3D3 commonly exhibit the excellent charge transport characteristics. In addition, the OTFT performance is improved with lengthening the alkyl chain in organic semiconductors, which can be attributed to the molecular orientation of semiconductors. On the other hand, non-alkylated DBTTT OTFTs with polar p(CEA-co-DEGDVE) show relatively poor electrical characteristics, while their performance is drastically enhanced with the alkylated DBTTTs. The ultraviolet photoelectron spectroscopy (UPS) reveals that surface polarity of the dielectric layer can be abated with alkyl chain in organic semiconductors. It is believed that this study can provide a useful insight to optimize dielectric/semiconductor interface to achieve high-performance OTFTs.

Performance enhancement of solution-processed p-type CuI TFTs by self-assembled monolayer treatment

Self-assembled monolayer (SAM) treatment of gate dielectrics plays a key role in the improvement of the electrical performance of organic thin-film transistors (TFTs) by reducing the interface traps. However, it is rarely explored in inorganic TFTs owing to possible irreversible damage to very thin SAMs during the sputtering and high-temperature annealing processes that are often used to deposit inorganic materials. Here, the feasibility of performance enhancement of inorganic p-type Zn-doped CuI TFTs is explored by a SAM treatment using 3-aminopropyltriethoxysilane (APTES) on the gate dielectric. Our result shows that the TFT performance is significantly enhanced with a 50% reduction in the interface trap density, a 326% increase in the hole mobility from 0.38 to 1.24 cm2V-1s-1and a 5-fold increase in the current on/off ratio from 2.6 × 106 to 1.1 × 107. In addition, the bias stress stability of the TFTs after the treatment is dramatically enhanced by a factor of 10 due to the improved interface properties. The threshold voltage shift is reduced from +19.6 to +1.8 V after 3600 s positive bias stress. The simple yet effective interface treatment approach may have great potential in the fabrication of high-performance inorganic p-type electronic devices.

Ultimate Limit in Optoelectronic Performances of Monolayer WSe2 Sloping-Channel Transistors.

Atomically thin monolayer two-dimensional (2D) semiconductors with natural immunity to short channel effects are promising candidates for sub-10 nm very large-scale integration technologies. Herein, the ultimate limit in optoelectronic performances of monolayer WSe2 field-effect transistors (FETs) is examined by constructing a sloping channel down to 6 nm. Using a simple scaling method compatible with current micro/nanofabrication technologies, we achieve a record high saturation current up to 1.3 mA/μm at room temperature, surpassing any reported monolayer 2D semiconductor transistors. Meanwhile, quasi-ballistic transport in WSe2 FETs is first demonstrated; the extracted high saturation velocity of 4.2 × 106 cm/s makes it suitable for extremely sensitive photodetectors. Furthermore, the photoresponse speed can be improved by reducing channel length due to an electric field-assisted detrapping process of photogenerated carriers in localized states. As a result, the sloping-channel device exhibits a faster response, higher detectivity, and additional polarization resolution ability compared to planar micrometer-scale devices.

Performance and stability of Al-doped HfGaO thin-film transistors deposited by vapor cooling condensation system

In this work, to study the features of Al atomic ratio in Al2O3-doped HfGaO (referred as AlHfGaO) channel layers of thin-film transistors, the HfGaO and various AlHfGaO films were deposited at approximately 80 K using a vapor cooling condensation system. The oxygen vacancy defects resided in AlHfGaO films and the defect density in the resulting thin-film transistors decreased with an increase of the Al atomic ratio. As defects reduced, threshold voltage and on/off current ratio increased, while threshold voltage offset and subthreshold swing decreased. In terms of the threshold voltage offset, measured by positive gate bias stress and negative gate bias stress methods, as the stability parameter of thin-film transistors, the stability was improved by using a higher Al atomic ratio in the AlHfGaO channel layers due to the suppression of the charge trapping effect.

Electrical properties and parameter analysis of all-solid-state LaZrO/InO electric double-layer transistors

All-solid-state electric double-layer (EDL) thin-film transistors (TFTs) consisting of solution-processed LaZrO gate insulators and sputtered InO channels with thicknesses of 10–200 nm were prepared, and their microstructures and electrical properties were investigated. In addition, mobility, carrier concentration, and their gate-voltage dependence in the InO layer were analyzed during a transistor operation to clarify the electron transport properties. It was confirmed that LaZrO was amorphous and that InO crystallized and had an In2O3 bixbyite structure. The transfer conductance increased with the InO thickness, and its normalized value was maximized (3.6 mS/V) at an InO thickness of 200 nm. The maximum capacitance of LaZrO was 31 μF/cm2, strongly suggesting the formation of an EDL. Solid EDL-TFTs operated stably without deterioration at gate voltages up to 5 V, which usually degrade liquid-electrolyte EDL transistors via electrolysis. Assuming the formation of a 1-nm-thick EDL, the concentration of carrier electrons induced during the transistor operation was estimated to be 1019–1021 cm−3. Moreover, the mobility increased with the InO thickness and reached a maximum value of 68 cm2/(V s) at an InO thickness of 120 nm. The conduction electrons were significantly affected by grain boundary scattering and surface scattering, in addition to scattering within the crystal grain. An increase in the InO thickness, which improved the crystallinity in the crystal grain, reduced the barrier height and the effect of grain boundary scattering.

Integrated internal ion-gated organic electrochemical transistors for stand-alone conformable bioelectronics.

Organic electronics can be biocompatible and conformable, enhancing the ability to interface with tissue. However, the limitations of speed and integration have, thus far, necessitated reliance on silicon-based technologies for advanced processing, data transmission and device powering. Here we create a stand-alone, conformable, fully organic bioelectronic device capable of realizing these functions. This device, vertical internal ion-gated organic electrochemical transistor (vIGT), is based on a transistor architecture that incorporates a vertical channel and a miniaturized hydration access conduit to enable megahertz-signal-range operation within densely packed integrated arrays in the absence of crosstalk. These transistors demonstrated long-term stability in physiologic media, and were used to generate high-performance integrated circuits. We leveraged the high-speed and low-voltage operation of vertical internal ion-gated organic electrochemical transistors to develop alternating-current-powered conformable circuitry to acquire and wirelessly communicate signals. The resultant stand-alone device was implanted in freely moving rodents to acquire, process and transmit neurophysiologic brain signals. Such fully organic devices have the potential to expand the utility and accessibility of bioelectronics to a wide range of clinical and societal applications.

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

AbstractWith continuous size scaling, the surface dangling bonds and short‐channel effects will degrade silicon based transistor performance. Thus, it is of great importance to seek new channel materials and transistor architectures to further continue Moore's law. Herein, a new ultra‐thin short‐channel tunneling transistor is developed comprising all 2D‐ components. Distinct from usual 2D planar transistor, this device is configured with vertical MoS2/WSe2 junction and in‐plane WSe2 channel, the switch states are realized by the gate‐regulated barrier height of heterojunction, enabling the transition of transport mechanism between thermionic‐emission and tunneling. Under dual‐gate configuration, the transistor exhibits high performance with drive current of 4.58 µA, on/off ratio of 4 × 107, subthreshold swing (SS) of 97 mV decade−1 and drain‐induced barrier lowering (DIBL) of 12 mV V−1, that can meet the requirement of logical applications in integrated circuits (IC). Taking advantage of the high‐speed tunneling current and unique short‐channel architecture, the device overcomes the issues of voltage spikes and long reverse recovery time that exist in usual electric components, and thus gains an access to the IC interface. This work provides a proof‐of‐concept transistor architecture relying on dual‐gate modulation, opening up a promising perspective for next generation low‐power, high‐density, and large‐scale IC technologies.

Improved Performance of Organic Light-Emitting Transistors Enabled by Polyurethane Gate Dielectric.

Organic light-emitting transistors (OLETs) are multifunctional optoelectronic devices that combine in a single structure the advantages of organic light-emitting diodes (OLEDs) and organic field-effect transistors (OFETs). However, low charge mobility and high threshold voltage are critical hurdles to practical OLET implementation. This work reports on the improvements obtained by using polyurethane films as a dielectric layer material in place of the standard poly(methyl methacrylate) (PMMA) in OLET devices. It was found that polyurethane drastically reduces the number of traps in the device, thereby improving electrical and optoelectronic device parameters. In addition, a model was developed to rationalize an anomalous behavior at the pinch-off voltage. Our findings represent a step forward to overcome the limiting factors of OLETs that prevent their use in commercial electronics by providing a simple route for low-bias device operation.

The Effect of Collector Region Design on Large-Signal Performance of Horizontal Current Bipolar Transistor (HCBT)

The impact of collector region design on large-signal performance of horizontal current bipolar transistor (HCBT) technology is investigated by calibrated time-domain load-pull measurements. Three representative high-performance devices of the same geometry but with different collector doping profiles, namely, uniform, n-well, and low-doped, are subjected to large-signal measurements wherein the radio frequency (RF) time-domain waveforms of current and voltage are measured to facilitate the determination of the maximum output power for each device. The extensive measurements outline the boundaries of the maximum collector current and voltage swings at RF determining linear operating area, which are a result of the physical phenomena in the high-current and high-voltage regimes, namely, the Kirk effect and impact ionization, respectively. While the highest-doped n-well HCBT provides the highest output power of 25.3 dBm at 1-dB gain compression, and the lowest-doped HCBT enables a wideband match at the collector, the HCBT with a uniform doping profile provides a tradeoff between the output power and bandwidth of the output match. The results show the versatility of HCBT technology as an alternative to CMOS and/or sillicon–germanium (SiGe) large-signal RF circuits for the front-ends (FEs) in the sub-6 GHz wireless communications range.

Enhancing electrical performance and stability of nanometer-thin ITO transistors via thermally oxidized alumina passivation layer

In this study, we investigated the utilization of alumina (AlOx), formed through the oxidation of thermally evaporated aluminum, as a passivation layer for nanometer-thin indium-tin-oxide (ITO) transistors. The ITO transistors passivated with thermally oxidized AlOx passivation exhibited remarkable electrical properties, with an average field-effect mobility of 241 cm2/Vs, significantly higher than the 40 cm2/Vs observed for devices without the AlOx passivation layer. Moreover, the passivated transistors maintained a high on/off current ratio at 108 level. In addition, the passivated transistors demonstrated improved stability, with a decrease in the threshold voltage (Vth) shift under negative bias stress testing conducted over 3600 seconds. The ITO transistors also displayed better air-ambient stability compared to transistors without the AlOx passivation layer. These results demonstrate the potential application of alumina passivation in nanometer-thin ITO field-effect transistors.

Editors’ Choice—Atomic Layer Etching of Tungsten Disulfide Using Remote Plasma-Induced Oxidation and Wet Etching

WS2 is an emerging semiconductor with potential applications in next-generation device architecture owing to its excellent electrical and physical properties. However, the presence of inevitable surface contaminants and oxide layers limits the performance of WS2-based field-effect transistors (FETs); therefore, novel methods are required to restore the pristine WS2 surface. In this study, the thickness of a WS2 layer was adjusted and its surface was restored to a pristine state by fabricating a recessed-channel structure through a combination of self-limiting remote plasma oxidation and KOH solution etching processes. The reaction between the KOH solution and WOX enabled layer-by-layer thickness control as the topmost oxide layer was selectively removed during the wet-etching process. The thickness of the WS2 layer decreased linearly with the number of recess cycles, and the vertical etch rate was estimated to be approximately 0.65 nm cycle−1. Micro-Raman spectroscopy and high-resolution transmission electron microscopy revealed that the layer-by-layer etching process had a nominal effect on the crystallinity of the underlying WS2 channel. Finally, the pristine state was recovered by removing ambient molecules and oxide layers from the surface of the WS2 channel, which resulted in a high-performance FET with a current on/off ratio greater than 106. This method, which provides a facile approach to restoring the pristine surfaces of transition-metal dichalcogenide (TMDC) semiconductors with precise thickness control, has potential applications in various fields such as TMDC-based (opto)electronic and sensor devices.

Enhancement-Mode GaN Transistor Technology for Harsh Environment Operation

This letter reports an enhancement-mode (E-mode) GaN transistor technology which has been demonstrated to operate in a simulated Venus environment (460 °C, ~ 92 atm., containing CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> etc.) for 10 days. The robustness of the W/p-GaN-gate AlGaN/GaN high electron mobility transistor (HEMT) was evaluated by two complementary approaches, (1) <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-situ</i> electrical characterization, which revealed proper transistor operation (including E-mode <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_TH</i> with < 0.09 V variation) in extreme environments; and (2) advanced microscopy investigation of the device after test, which highlighted the effect of the stress conditions on the epitaxial and device structures. To the best of the authors’ knowledge, this is the first demonstration and comprehensive analysis of E-mode GaN transistors in such harsh environments, therefore establishing the proposed GaN technology as a strong contender for harsh environment mixed-signal electronics.