Performance Of Thin-film Transistors Research Articles

Long‐Channel Effects in Randomly Oriented Carbon Nanotube Thin Film Transistors

AbstractCarbon nanotube (CNT) thin film transistors (TFTs) have demonstrated great potential for application in highly sensitive biosensors and large‐area electronics. However, research on the electrical behavior of long‐channel CNT TFTs is lacking; thus, the purposeful improvement in the performance of biosensors or circuits is difficult. In this study, the electrical transport characteristics of ionic‐liquid‐gate CNT TFTs with channel lengths (Lch) ranging from 10 to 400 µm are investigated. The CNT TFTs present classical drift‐diffusion transport at on‐state with a carrier mobility of around 27 cm2 V−1 s−1. In the subthreshold region of the CNT TFTs, an abnormal Lch‐dependent subthreshold swing (SS) relationship, named as the long‐channel effect (LCE)is observed, where SS worsens with increasing Lch. The existence of the junctions between the CNTs results in an unconventional density of states for carriers and a large series resistance for sharing the gate voltage; this dominates the abnormal scaling behavior in the subthreshold region by degrading the electrostatic integrity. The discovery of the abnormal LCE can aid in the construction of device models and purposefully improve the performance of CNT TFTs for biosensors and other large‐scale electronic applications.

Comparative Study of Atomic Layer Deposition Supercycle Design Effects on Reliability in Heterogeneous IGZO Channel TFTs

Oxide semiconductor thin-film transistors (TFTs) are promising candidates for application in display backplanes and memory devices. To ensure both high performance and stable electrical properties of oxide TFTs over long-term use, superior mobility and device stability need to be obtained. In this regard, atomic layer deposition (ALD) has gained attention as a facile method for obtaining conformal oxide films under defect-free conditions and adjusting the composition or distribution for targeted TFT performance. Here, we propose that, even with the same bulk composition, variations in the local composition using an ALD supercycle design can significantly affect the TFT performance, particularly the bias-temperature stability. To ascertain the influence of the local cation distribution on the performance, we compared two supercycle designs by reversing the sub-cycles of indium, gallium, and zinc with identical bulk In–Ga–Zn ratios. Despite minimal changes in the electrical characteristics, such as the mobility and threshold voltage, of the two TFTs designed with ALD supercycles, there was a significant difference in their reliability. Devices with an indium-rich IGZO active layer on the back channel exhibited a hump phenomenon and approximately five times greater Vth degradation (ΔVth: -0.67 V to -3.36 V). By conducting an additional case study of IGZO TFTs and film analysis, we confirmed that mobility is largely governed by the bulk composition, whereas the local surface composition, serving as the back channel, is the key to reliability. The device performance results could be confirmed through the surface and bulk analyses of heterogeneous films engineered through the ALD supercycle design. Furthermore, it has been proposed that optimizing the ALD supercycle design is the key to obtaining high-performance oxide semiconductor TFTs.

Saturation Mobility of 100 cm2 V-1 s-1 in ZnO Thin-Film Transistors through Quantum Confinement by a Nanoscale In2O3 Interlayer Using Spray Pyrolysis.

In this study, we present a comprehensive study on the fabrication and characterization of heterojunction In2O3/ZnO thin-film transistors (TFTs) aimed at exploiting the quantum confinement effect to enhance device performance. By systematically optimizing the thickness of the crystalline In2O3 (c-In2O3) layer to create a narrow quantum well, we observed a significant increase in saturation mobility (μSAT) from 12.76 to 97.37 cm2 V-1 s-1. This enhancement, attributed to quantum confinement, was achieved through the deposition of a 3 nm c-In2O3 semiconductor via spray pyrolysis. Various In2O3 layer thicknesses (2-5 nm) were obtained by adjusting precursor solution concentration, flow rate, and number of spray cycles. Post annealing treatments were employed to reduce the defects at the interface and within the oxide film, enhancing device stability and performance. Transmission electron microscopy (TEM) confirmed the uniformity of the c-In2O3 film thickness, while variations in thickness significantly influenced TFT performance, particularly the turn-on voltage (VGS) due to changes in the carrier concentration. Ultraviolet photoelectron spectroscopy (UPS) and X-ray photoelectron spectroscopy (XPS) supported the formation of a potential well with a two-dimensional electron gas (2DEG). The study of single and multiple superlattice structures of consecutive c-In2O3 and c-ZnO layers provided insights into the effects of multiple quantum wells on the TFT performance. This research presents an advanced approach to TFT optimization, highlighting high reliability, and environmental and bias stabilities. These lead to enhanced mobility and performance uniformity through the precise control of c-In2O3 layer thickness for the quantum confinement effect.

Understanding thickness-dependent stability of tungsten-doped indium oxide transistors

In this study, the influence of the thickness of the channel layer on the electrical properties and stability of tungsten-doped indium oxide (IWO) thin-film transistors (TFTs) was investigated. Although oxide-semiconductor TFTs, particularly indium gallium zinc oxide, are promising, problems related to oxygen vacancies have led to their instability. In contrast, IWO has proven to be a compelling alternative because of its robust resistance to oxygen vacancies. IWO TFTs with varying channel thicknesses (10, 20, and 30 nm) were fabricated, and the device parameters, such as threshold voltage (Vth), subthreshold swing (SS), field-effect mobility (μFE), and on/off current ratio (Ion/Ioff), were analyzed. It was found that as the channel thickness increased, Vth exhibited a negative shift and SS increased, indicating an increase in carrier concentration. This phenomenon is attributed to the bulk trap density, in particular to oxygen vacancies. Negative bias stress tests confirmed the influence of the oxygen vacancies, with thicker channels showing more pronounced shifts. Low-frequency noise measurements were consistent with the carrier number fluctuation model, indicating that defects within the channel region contribute to the observed noise. The study concludes that identifying an optimal channel thickness during device manufacturing is crucial for improved TFT performance, with 20 nm devices characterized by high μFE and comparable trap density to 10 nm. This study provides valuable insight into the nuanced relationship between the channel thickness, trap density, and electrical performance of IWO TFTs.

Thermal atomic layer deposition-processed InHfZnO thin film transistors with excellent stability

In recent years, the downscaling of transistors has sparked considerable interest in the advancement of amorphous oxide semiconductors, particularly indium-hafnium-zinc oxide (IHZO) has remarkable potential in applications such as high-resolution displays and 3D NAND. For the first time, we propose the fabrication of IHZO thin film transistors (TFTs) via thermal atomic layer deposition (TH-ALD). The preparation, electrical properties, and stability of IHZO TFTs are investigated. The performance of TFT deposited at 250 °C and annealed in N2 atmosphere at 300 °C exhibits a high field-effect mobility (μ) of 22.53 cm2/Vs, a high Ion/Ioff of ∼107, a low threshold voltage (Vth) of 0.15 V, and a minimum subthreshold swing (SS) of 0.24 V/decade. Furthermore, the threshold voltage shifts (ΔVth) in TFTs annealed in N2 and O2 are 0.31 and 0.16 V, respectively. These enhancements are attributed to the defects suppression and remaining ionized oxygen vacancies result in increased electron concentration in N2-annealed films. In comparison, O2 annealing causes a reduction in field effect mobility but concurrently enhances stability due to the direct passivation of defects, which leads to fewer oxygen vacancies. Additionally, Hf content can also impact the performance of TFT devices, even a small addition of Hf also results in the effective reduction of the carrier concentration. These findings provide valuable insights into the device mechanism of IHZO TFTs, presenting a novel avenue for comprehending and augmenting their overall performance.

DC and AC Performance of InGaZnO Thin-Film Transistors on Flexible PEEK Substrate

DC and AC Performance of InGaZnO Thin-Film Transistors on Flexible PEEK Substrate

Improving TFT Device Performance by Changing the Thickness of the LZTO/ZTO Dual Active Layer.

The primary objective of this research paper is to explore strategies for enhancing the electrical performance of dual active layer thin film transistors (TFTs) utilizing LZTO/ZTO as the bilayer architecture. By systematically adjusting the thickness of the active layers, we achieved significant improvements in the performance of the LZTO/ZTO TFTs. An XPS analysis was performed to elucidate the impact of the varying O2 element distribution ratio within the LZTO/ZTO bilayer thin film on the TFTs performance, which was directly influenced by the modification in the active layer thickness. Furthermore, we utilized atomic force microscopy to analyze the effect of altering the active layer thickness on the surface roughness of the LZTO/ZTO bilayer film and the impact of this roughness on the TFTs electrical performance. Through the optimization of the ZTO active layer thickness, the LZTO/ZTO TFT exhibited an mobility of 10.26 cm2 V-1 s-1 and a switching current ratio of 5.7 × 107, thus highlighting the effectiveness of our approach in enhancing the electrical characteristics of the TFT device.

Amorphous InZnSnO thin-film-transistors performance enhancement with low-energy Xenon Pulsed-light annealing

The electrical characteristics and stability of amorphous indium-zinc-tin oxide (IZTO) thin-film transistors (TFTs) were significantly improved in this study using low-energy Xenon pulsed-light annealing (PLA). In comparison to conventional furnace annealing (FA), PLA treatment significantly reduced the processing temperature and annealing time. Besides, the defect states are obviously reduced from 1.73×1012 cm-2 to 6.53×1011 cm-2 by PLA treatment, resulting in improved device electrical characteristics and enhanced reliability, including improved carrier mobility from 20.08 to 39.61 cm2/V∙s, threshold voltage from 0.82 to 0.24 V, subthreshold swing (S.S.) from 0.54 to 0.24 V/decade, and the ON/OFF current ratio from 2.32×107 to 7.31×108. In addition, the enhanced stability is observed under both positive gate-bias stress (PGBS) of VGS = 30 V and negative gate-bias stress (NGBS) of VGS = –30 V for a stress duration of 3000 s. The threshold voltage shift (ΔVTH) is reduced from 8.31 V to 1.65 V and from –3.93 V to –1.51 V, respectively. This is the first time low-energy PLA was conducted for IZTO TFT performance improvement.

Plasma-enhanced atomic layer deposition of indium-free ZnSnOx thin films for thin-film transistors

An appropriate synthesis technique for growing high-quality indium-free ZnSnOx (ZTO) films should be developed to achieve high-performance thin-film transistors (TFTs) utilizing ZTO films. This study investigated the growth characteristics and electrical properties of ZTO thin films grown via plasma-enhanced atomic layer deposition (PEALD) using bis(1-dimethylamino-2-methyl-2-propoxide)Sn, diethylzinc, and O2 plasma to optimize the composition and enhance the device performance. Deviations were observed in the growth per cycle when using PEALD for ZTO, compared with binary oxides. In the PEALD of the ZTO films, the introduction of the SnO2 sub-cycle enhanced the mass gain in the ZnO sub-cycle, whereas the mass gain in the SnO2 sub-cycle decreased with the addition of the ZnO sub-cycle. This was attributed to changes in the density of the functional groups on the reaction surface. Precise control over the composition was achieved, enabling the identification of the optimal Zn58Sn42Ox composition. Post-deposition annealing significantly improved the TFT performance, with devices showing enhanced mobility, positive shifts in the threshold voltage, and reduced subthreshold swing values. These improvements stemmed from reductions in oxygen vacancies and sub-gap defect states. These findings highlight the potential of PEALD-grown ZTO films for use in high-performance, cost-effective TFTs, facilitating their integration into modern semiconductor electronics.

Impact of Crystal Domain on Electrical Performance and Bending Durability of Flexible Organic Thin-Film Transistors with diF-TES-ADT Semiconductor

Impact of Crystal Domain on Electrical Performance and Bending Durability of Flexible Organic Thin-Film Transistors with diF-TES-ADT Semiconductor

Enhanced electrical performance and stability of solution-processed oxide semiconductor thin-film transistors via an incorporation of deionized water oxidizer

Solution-processed amorphous oxide semiconductor thin films contain poor metal-oxygen-metal (M-O-M) networks and numerous impurities, making it difficult to manufacture high-performance semiconductor devices with excellent stability. In this study, we enhance the electrical performance and device stability of solution-processed oxide thin-film transistors (TFTs) by incorporating water molecular oxidants. In solution, a water molecule can be easily incorporated by adding deionized water (DW) to the precursor solution. The DW-incorporated precursor solutions induced the production of oxide semiconductor thin films with improved M-O-M networks and fewer defect states. Therefore, compared to conventional case, the DW-incorporated indium zinc oxide (InZnO) TFT showed improved device performances and significantly reduced changes of threshold voltage under positive gate bias stress and negative gate bias/illumination stress conditions. This approach of incorporating DW into the precursor solutions provides a promising route for fabricating high-quality amorphous semiconductor films and transistor devices.

Quantitative Insight of Annealing Atmosphere-Induced Device Performance and Bias Stability in a Ga-Doped InZnSnO Thin-Film Transistors

Quantitative Insight of Annealing Atmosphere-Induced Device Performance and Bias Stability in a Ga-Doped InZnSnO Thin-Film Transistors

Viable Approach of Tuning Oxide Semiconductor Thin Films in Solution‐Processed Heterojunction Thin Films Transistors for Both Higher Performances and Stability

AbstractMetal‐oxide thin‐film transistors (TFTs) have garnered much attention because of their advantages such as high transparency, low leakage current, and low processing temperature. However, there is a need to continuously improve their mobility and bias stability for application to next‐generation advanced electronics. In this study, the thickness of bilayer semiconductors is finely controlled to enhance the charge transport characteristics and bias stability in solution‐processed heterojunction oxide TFTs. The thicknesses of the top and bottom layers in the bilayer are individually adjusted by controlling solution molarity. The introduction of a bilayer channel improved the electrical performance of oxide TFTs via effective charge transport. However, trap‐limited conduction becomes dominant in the bilayer with an excessively thick top layer, thereby leading to a significant reduction in mobility and positive bias stability. Meanwhile, although increasing the bottom layer thickness contributes to improved mobility and reliability, it causes a serious negative shift in threshold voltage (VTH). TFTs with an optimized bilayer structure show high mobility at a VTH close to 0 V and have particularly excellent positive bias stress stability. This study on bilayer channel thickness will be beneficial for developing advanced transistors with optimized bilayer or multilayer channels.

Passivated indium oxide thin-film transistors with high field-effect mobility (128.3 cm2 V−1 s−1) and low thermal budget (200 °C)

Here, we demonstrate a high-mobility indium oxide (In2O3) thin-film transistor (TFT) with a sputtered alumina (Al2O3) passivation layer (PVL) with a low thermal budget (200 °C). The sputtering process of the Al2O3 PVL plays a positive role in improving the field-effect mobility (µ FE) and current on/off ratio (I ON/I OFF) performance of the In2O3 TFTs. However, these enhancements are limited due to the high density of intrinsic trap defects in the In2O3 channels, as reflected in their large hysteresis and poor bias stability. Treating the In2O3 channel with oxygen (O2) plasma prior to sputtering the Al2O3 PVL results in notable improvements. Specifically, a high µ FE of 128.3 cm2V−1 s−1, a high I ON/I OFF over 106 at V DS of 0.1 V, a small hysteresis of 0.03 V, and a negligible threshold voltage shift under negative bias stress are achieved in the passivated In2O3 TFT (with O2 plasma pretreatment), representing a significant improvement compared to the passivated In2O3 TFT (without O2 plasma pretreatment) and the unpassivated In2O3 TFT. The remarkable reduction of intrinsic trap defects in the passivated In2O3 TFT compensated by O2 plasma is the primary mechanism underlying the improvement in µ FE and bias stability, as validated by x-ray photoelectron spectra, hysteresis analysis, and temperature-stress electrical characterizations. Plasma treatment effectively compensates for intrinsic trap defects in oxide semiconductor (OS) channels, when combined with sputter passivation, resulting in a significant enhancement of the overall performance of OS TFTs under low thermal budgets. This approach offers valuable insights into advancing OS TFTs with satisfactory driving capability and wide applicability.

Sputtered AlOx interlayer for improving performance of a-InGaZnO TFTs: A study on hydrogen diffusion mitigation and electron modulation

In this study, we developed an a-InGaZnO (a-IGZO) thin film transistor (TFT) structure that inserts a sputtered AlOx intermediate layer (IL) within the active layer. The IL not only effectively blocks hydrogen (H) diffusion from the gate insulation (GI) layer to the upper region of a-IGZO but also modifies the energy band structure of the bottom channel region and creates a locally low electron concentration that counteracts the excess electron donated by diffused H. Compared to conventional TFTs, the TFT with the IL exhibits impressive electrical characteristics, including a high saturation mobility (μsat) of 14.5 cm2 V−1 s−1, an on/off current ratio (Ion/Ioff) of 6.2 × 108, and a low subthreshold swing (SS) of 0.16 V/dec. Furthermore, this structure exhibits remarkable stability under negative bias stress and negative bias illumination stress, with ΔVth values of 1.1 and 1.5 V, respectively. The integration of the IL provides a promising approach for enhancing the performance of a-IGZO TFTs, paving the way for next-generation display technologies.

A normally off high-voltage InGaZnO transistor with drain offset region modulated by an InZnO layer

This work presents a normally off high-voltage indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) featuring a drain offset region modulated by the IZO layer (IMO, IMO-IGZO TFT). In addition to decreasing the specific on-resistance (Ron,sp) by more than three orders of magnitude, the IMO structure further elevates the breakdown voltage by optimizing the thickness of the IZO layer (tIZO) compared to the Offset TFT. Through TCAD simulation, the underlying mechanism responsible for the improved performance of the IMO-IGZO TFT is elucidated. The introduced IZO modulating layer effectively increases carrier concentration and rebuilds the electric field within the offset region. Consequently, the IMO-IGZO TFT with a 6 nm thick IZO modulating layer and 3.5 μm length offset region attains a breakdown voltage of 410 V and demonstrates favorable Ron,sp of 5.3 × 103 mΩ × cm2. This results in a Baliga's figure of merit of 31.72 kW/cm2, surpassing conventional and Offset TFTs by factors of 186 and 3048, respectively.

Enhanced Performance of P-Channel CuIBr Thin-Film Transistor by ITO Surface Charge-Transfer Doping.

The process development and optimization of p-type semiconductors and p-channel thin-film transistors (TFTs) are essential for the development of high-performance circuits. In this study, the Br-doped CuI (CuIBr) TFTs are proposed by the solution process to control copper vacancy generation and suppress excess holes formation in p-type CuI films and improve current modulation capabilities for CuI TFTs. The CuIBr films exhibit a uniform surface morphology and good crystalline quality. The on/off current (ION/IOFF) ratio of CuIBr TFTs increased from 103 to 106 with an increase in the Br doping ratio from 0 to 15%. Furthermore, the performance and operational stability of CuIBr TFTs are significantly enhanced by indium tin oxide (ITO) surface charge-transfer doping. The results obtained from the first-principles calculations well explain the electron-doping effect of ITO overlayer in CuIBr TFT. Eventually, the CuIBr TFT with 15% Br content exhibits a high ION/IOFF ratio of 3 × 106 and a high hole field-effect mobility (μFE) of 7.0 cm2 V-1 s-1. The band-like charge transport in CuIBr TFT is confirmed by the temperature-dependent measurement. This study paves the way for the realization of transparent complementary circuits and wearable electronics.

Enhancing the Stability and Mobility of TFTs via Indium-Tungsten Oxide and Zinc Oxide Engineered Heterojunction Channels Annealed in Oxygen Ambient.

This study demonstrates a significant enhancement in the performance of thin-film transistors (TFTs) in terms of stability and mobility by combining indium-tungsten oxide (IWO) and zinc oxide (ZnO). IWO/ZnO heterojunction structures were fabricated with different channel thickness ratios and annealing environments. The IWO (5 nm)/ZnO (45 nm) TFT, annealed in O2 ambient, exhibited a high mobility of 26.28 cm2/V·s and a maximum drain current of 1.54 μA at a drain voltage of 10 V, outperforming the single-channel ZnO TFT, with values of 3.8 cm2/V·s and 28.08 nA. This mobility enhancement is attributed to the formation of potential wells at the IWO/ZnO junction, resulting in charge accumulation and improved percolation conduction. The engineered heterojunction channel demonstrated superior stability under positive and negative gate bias stresses compared to the single ZnO channel. The analysis of O 1s spectra showed OI, OII, and OIII peaks, confirming the theoretical mechanism. A bias temperature stress test revealed superior charge-trapping time characteristics at temperatures of 25, 55, and 85 °C compared with the single ZnO channel. The proposed IWO/ZnO heterojunction channel overcomes the limitations of the single ZnO channel and presents an attractive approach for developing TFT-based devices having excellent stability and enhanced mobility.

Enhanced Electrical Properties and Stability in IGZO TFTs via Low-Temperature Activation with MgOx Layer.

We propose the introduction of a magnesium oxide (MgOx) layer to reduce the temperature required for the activation of indium gallium zinc oxide (IGZO) thin films. By incorporating the MgOx layer between the IGZO channel layer and the gate insulator layer, the required activation temperature is lowered from 300 to 200 °C while enhancing the electrical performance of the IGZO thin-film transistor (TFT). Specifically, the field effect mobility is improved from 6.40 to 16.12 cm2/(V s), the on/off current ratio is enhanced from 1.62 × 109 to 7.16 × 109, and subthreshold swing is enhanced from 0.48 to 0.46 V/decade. Furthermore, IGZO TFTs with the MgOx layer exhibit enhancements in threshold voltage (VTH) shift compared to TFTs without the MgOx layer under positive bias stress (VGS = 20 V and VDS = 0.1 V for 10,000 s) and negative bias stress (VGS = -20 V and VDS = 0.1 V for 10,000 s): the VTH shifts are decreased from 2.40 to 1.72 V and from 0.56 to 0.53 V, respectively. These enhancements are verified through various analyses and are attributed to the diffusion of Mg atoms into the IGZO front channel during the low-temperature activation process, which results in the formation of Mg-doped IGZO between the MgOx and IGZO channel layers.

Study of geometry effect on the performance of thin-film transistors fabricated with ZnGa2O4 epilayer grown by metalorganic chemical vapor deposition for high voltage applications

Enhancement mode thin film transistors (TFTs) having different geometries were fabricated on the Zinc gallium oxide (ZnGa2O4) epilayer grown on a c-plane sapphire substrate by metalorganic chemical vapor deposition (MOCVD). A field emission scanning electron microscope, atomic force microscopy, and X-ray diffraction were employed to conduct a detailed analysis of the film composition, morphology, and crystal structure. The distance between the source-to-gate and gate length was kept to be 7 μm and 3 μm in all the devices with varying gate-to-drain lengths of 10, 20, and 30 μm. Moreover, neutral beam etching technology was employed to isolate the individual devices and reduce the defects induced by plasma etching. It was found that the threshold voltage changes from 6 V to 7.6 V with the increase in source to drain length from 20 μm to 40 μm. The On/Off ratio of the devices was found to be 105, with a maximum current around 1 μA/mm. Additionally, the device breakdown voltage increased from 240 V to about 656 V with the increase in the device length. The results demonstrate the fabrication of the high breakdown voltage ZnGa2O4-based TFT and establish the co-relation of the source to drain length with the device characteristics.