Performance Of SRAM Cell Research Articles

Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors

Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors

Comparison between Power Dissipation and Propagation Delay on 6T SRAM Cell Design Using GDI Logic with Transmission Gate VMSA and Voltage Divider

The rapid evolution of the semiconductor industry has witnessed shrinking portable and mobile devices alongside an increasing demand for extended battery life. Addressing the critical challenges of speed and battery life in digital devices, this paper investigated the effectiveness of innovative low-power design techniques. Focusing on the Gate Diffusion Input (GDI) approach, a recent advancement in the field, a comprehensive analysis revealed its significant potential for reducing power consumption in digital circuits. Additionally, a comparative analysis was conducted to evaluate the performance of conventional 6T GDI SRAM cells and their Modified 6T GDI SRAM with Voltage Divider, considering the influence of Sense Amplifiers. Simulation data demonstrated that Modified 6T SRAM designs, particularly the Voltage Divider and TGVMSA variants, achieved significantly lower power dissipation and delay despite having a larger cell area. Remarkably, the proposed design substantially improved power dissipation and propagation delay, achieving 1.3 ps, and 889.41mV at 1.8V shows that the suggested design enhances power dissipation and propagation delay. These findings suggest that the proposed design offers a promising strategy for enhancing power efficiency and performance in digital devices, thereby mitigating the limitations of battery life and speed in the modern technological landscape.

Design of radiation-hardened memory cell by polar design for space applications

This paper proposed a radiation-hardened memory cell (RHMC12T) by polar design for space applications. The proposed cell has the following advantages: (1) it can tolerate all single-node upset and partial double-node upset based on combining radiation hardened by polar design technology together with reasonable layout topology; (2) comparing with the state-of-the-art radiation hardened SRAM cells, simulation results show the proposed RHMC12T cell has lower write access time, higher wordline write trip voltage, larger static noise margin, and larger critical charge. And Monte Carlo simulation results have shown that RHMC12T has good robustness; (3) electrical quality metric is widely used to evaluate the overall performance of SRAM cells. And RHMC12T has the largest EQM compared with the state-of-the-art radiation hardened SRAM cells, which suggests the proposed RHMC12T exhibits good circuit performance (including write/read access time, static noise margin et al.) as well as good radiation resistance performance with sacrificing a large area overhead.

Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques

This paper presents the sleepy keeper and drain gating technique to improve the performance of 10T SRAM cell. The behavior of 10T SRAM cell is evaluated using benchmarked industry standard GPDK 45nm Technology Node of the Cadence Virtuoso EDA tool. The performance is analyzed in terms of dynamic and static parameters of 10T SRAM cell and compared with 6T SRAM, where find the reduction in dynamic power and static power dissipation. Besides this, observed the reduction in leakage current using sleepy keeper and drain gating technique. The proposed modified topology applicable in single-ended write and differential read operation. The read delay product and the write delay product is decreased by 36.7 % and 67.5 %, respectively. The major goal of the suggested architecture is to provide the improved stability, reduction in delay, as well as reduction in leakage current.

Performance investigation of Ge DLTFET based digital integrated circuit

ABSTRACT The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications.

Performance and Area Optimization of SRAM Cell in Nanocomputing Application

Performance and Area Optimization of SRAM Cell in Nanocomputing Application

Robust Low Power Transmission Gate (TG) based 9T SRAM cell with Isolated Read and Write Operation

Stability and performance of conventional SRAM cells operating at low voltages are severely affected due to enhanced process variations. This paper proposes a Transmission Gate (TG) based 9T SRAM cell with independent read/write operation and compares its performance with 6T, 8T, and 10T SRAM cells. The enhanced read and write ability of the cell is due to the selective use of positive feedback loop. To show the efficacy of the proposed technique, simulations are carried out using 130nm UMC technology files on Cadence Virtuoso and HSPICE. The transistor size with minimum length and width is used in each configuration using the UMC 130nm technology file for all the simulations. Various body biasing techniques (Reverse Body Bias and Forward Body Bias) are applied to reduce active and standby power. It has been observed that the proposed cell shows better results in terms of enhanced read, write and hold stability and for reduced power also. Further, the write access time is less for the proposed cell. The layout of the proposed architecture is also shown.

Design of an enhanced write stability, high-performance, low power 11T SRAM cell

ABSTRACT In the present era of diminishing technology nodes, stability and performance of SRAM cells deteriorate. To cope up with the above growing concerns, a new 11 T SRAM cell has been proposed which improves the stability in all operating modes of SRAM as well as the delay and power in the write mode. At worst process corner SS, the write 0 delay has been improved by 14.01%, 6.75%, 115.72% and 26.61% compared to 6 T, 8 TG, 10 TDiff and 11 T SRAM designs and write 1 delay has been improved by 9.2%, 88.639%, 13.69% and 71.42% compared to 6 T, 10 TDiff, DDS11T and 11 T designs at 0.9 V supply voltage. The impact of PVT variations has been studied on SNM, Write Margin, Read & Write delay, Leakage Power. The Monte Carlo simulation has been performed to study the effect of variability. P11T SRAM cell exhibits narrower spread in the distribution of majority design metrics. The removal of the half-select issue has been illustrated in the P11T SRAM cell using Monte Carlo simulations. Post-Layout simulation has been carried out to evaluate different design metrics at 45 nm technology node in Cadence Virtuoso.

Full-VDD and near-threshold performance of 8T FinFET SRAM cells

We evaluate full-VDD and near-threshold operation of nine novel eight-transistor (8T) FinFET SRAM cell schemes using shorted gate (SG) and low power FinFET configurations for 32-bit by 1024-word SRAMs. 8T SRAM schemes outperform six-transistor schemes since SG-configured read FinFETs minimize delay and reverse-biased inverter FinFETs’ back gates reduce leakage current by up to 97%. At near-threshold, 8T FinFET cell delay increases by 56%, but leakage current and energy-delay product (EDP) decrease by up to 16% and 77%, respectively. 8T Low-Power Inverters scheme uses these configurations and reduces EDP by 60% (79% at near-threshold) versus the conventional SG 8T FinFET SRAM.

Leakage Characterization of a Novel Transmission Gate based 10T SRAM Cell

In this paper, a novel transmission gate based 10 transistor (TG 10T) SRAM cell is proposed. Read and write bit lines are decoupled in the proposed cell and single bit line write scheme with loop-cutting is employed in the TG 10T SRAM cell to reduce active power consumption during the write operation. Proposed TG 10T and conventional six transistors (6T) SRAM cells are simulated using TSMC based 90nm CMOS technology. Transmission gate is used at bit line side to improve readability of both =0‘ and =1‘ output and at the word line side to improve write ability of both =0‘ and =1‘. Although the proposed cell incurs area penalty in terms of four transistors (43.39%), the leakage performance of the TG 10T SRAM cell is better for both gate and subthreshold leakage when compared with conventional 6T SRAM cell.

Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits

In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors for ultra-low voltage operation. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides significant improvement in SRAM stability, Vmin and performance. The stability and performance of the proposed cell are evaluated and compared with the conventional MOSFET 8T cell and pure TFET 8T cell using mixed-mode TCAD simulations based on published design rules for 22 nm technology node. Besides, the impacts of the device design of the proposed SRAM cell on the stability are also investigated. Various write-assist techniques to enhance the write-ability across VDD= 0.2 to 0.7 V for these SRAM cells are comparatively assessed. The results indicate that the proposed mixed TFET-MOSFET cell topology is viable for ultra-low voltage operation while MOSFET cell provides better stability and performance for high voltage operation.

Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells

The threshold voltage drifts induced by positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) weaken nMOS and pMOS, respectively. These long-term aging threshold voltage drifts degrade SRAM cell stability, margin, and performance. This paper presents a low area overhead adaptive body bias (ABB) circuit that compensates BTI aging effects and also improves performance of an aged SRAM cell. The proposed circuit uses a control circuit and word line voltage to control the voltage applied to the body of 6T SRAM cell's transistors such that the BTI effect dependence of threshold voltage is reduced. In the worst case, the proposed ABB reduces the HOLD SNM degradation by 6.85%, the READ SNM degradation by 12.24%, the WRITE margin degradation by 2.16%, the READ delay by 28.68%, and the WRITE delay by 32.61% compared to the conventional SRAM cell at 108 s aging time.

Effect of phase of noise on the performance of 6T SRAM cell

In this paper a detailed study of the effect of the phase of noise has been done on 6T SRAM cell. The 6T SRAM has been subjected to different combinations of noises at the storage nodes and the read ability and write ability of the SRAM cell is examined considering different noise voltage levels. It is found that the effect is different under different combinations of the phases of the noise voltages.

Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-$\kappa$ Metal-Gate Devices

The threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) drifts induced by negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. These long-term <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> drifts degrade SRAM cell stability, margin, and performance, and may lead to functional failure over the life of usage. Meanwhile, the contact resistance of CMOS device increases sharply with technology scaling, especially in SRAM cells with minimum size and/or sub-ground rule devices. The contact resistance, together with NBTI/PBTI, cumulatively worsens the SRAM stability, and leads to severe SRAM performance degradation. Furthermore, most state-of-the-art SRAMs are designed with power-gating structures to reduce leakage currents in Standby or Sleep mode. The power switches could suffer NBTI or PBTI degradation and have large contact resistances. This paper presents a comprehensive analysis on the impacts of NBTI and PBTI on power-gated SRAM arrays with high-k metal-gate devices and the combined effects with the contact resistance on SRAM cell stability, margin, and performance. NBTI/PBTI tolerant sense amplifier structures are also discussed.

Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node

The performance and threshold voltage variability of quasi-planar bulk MOSFETs are compared against those of conventional bulk MOSFETs, via three-dimensional (3-D) device simulations with gate line-edge roughness and atomistic doping profiles, at 25 nm gate length. The nominal performance of six transistor (6-T) SRAM cells is studied via 3-D simulation of full cell structures. Compact (analytical) modeling is used to estimate SRAM cell yields. As compared to conventional bulk CMOS technology, quasi-planar bulk CMOS technology provides for enhanced SRAM cell performance and yield, and hence facilitates reductions in cell area and operating voltage. It also enables a notchless 6-T SRAM cell design which is advantageous for improved lithographic printability and either smaller area or lower standby power, and is projected to achieve 6-sigma cell yields at operating voltages down to ~0.8 V.

Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect

In this paper the analysis of SNM, RNM, WNM and static power variation with width of access, load and driver have been carried out for nanoscale FinFET based SRAM cell. FinFET based SRAM design has been proposed as an alternative solution to the bulk devices. It can be inferred from the results that with increase in the width of driver FinFET, the high SNM reduces and low SNM increases. This is due the fact that the leakage current is considerably reduced due to increased control of the FinFET device structure, resulting relatively in highIon/Ioffratio. Further, the effect of process variation on the SRAM cell performance was analyzed using Monte Carlo simulation on HSPICE. The Monte Carlo simulation results for RNM and WNM to quantify the effect of process variation arising due to variation in FinFET's widths. The simulation was carried out for 1000 values, assuming 3σ equal to 10% of the mean value. Two structures of the FinFET viz. the standard PTM model and an underlapped FinFET have been also used for the simulations. It was identified that while the relative levels of the noise margins were lower for the underlapped case, the standard deviation was considerably lower too. In this work we also analyze the effect of temperature on noise margins and static power for FinFET based SRAM cell. FinFET is suitable for future nanoscale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current.

Impact of RDF and RTS on the performance of SRAM cells

This paper investigates electrical effects due to reliability phenomena associated with the downscaling of transistors in advanced technologies, particularly Random Telegraph Signal (RTS) and Random Dopant Fluctuations (RDF). RDF and RTS are becoming important issues in sub-60 nm technologies, mainly in memories, where transistor sizes are smaller. This paper presents a comprehensive evaluation of the impact of the joint effect of RTS and RDF on 6T-SRAM cells. Based on 3-D atomistic simulation of the device structure, doping profile, and trap location, the random threshold voltage variation caused by the joint effect of RDF and RTS is evaluated. The derived threshold voltage variation is then used to statistically evaluate the performance variation at the circuit level. Finally, the impact of assuming a normal distribution for the threshold voltage variation caused by RDF and RTS is studied. The results obtained running Monte Carlo simulations raffling the value of the variation of the threshold voltage from a database obtained by 3-D atomistic simulation are compared to the results obtained running Monte Carlo simulations considering the variation of the threshold voltage as a Normal distribution. The results show that for a 6T-SRAM designed with 45 nm technology the read noise margin distributions are very similar between the two cases, making the Normal distribution a good approximation for the V th variations. Nevertheless, the performance variation induced at the circuit level does not necessarily follow a normal distribution.

Variability Analysis of TiN FinFET SRAM Cells and Its Compensation by Independent-DG FinFETs

The variability of the TiN FinFET SRAM cell performance is analyzed. It is experimentally demonstrated that the Vth-controllable independent-double-gate (IDG) FinFET technology successfully improves the variation problems in SRAM performance. As a result, the IDG-FinFET technology enables 0.5-V SRAM operation with high cell stability.

Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared.