Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node

Abstract

The performance and threshold voltage variability of quasi-planar bulk MOSFETs are compared against those of conventional bulk MOSFETs, via three-dimensional (3-D) device simulations with gate line-edge roughness and atomistic doping profiles, at 25 nm gate length. The nominal performance of six transistor (6-T) SRAM cells is studied via 3-D simulation of full cell structures. Compact (analytical) modeling is used to estimate SRAM cell yields. As compared to conventional bulk CMOS technology, quasi-planar bulk CMOS technology provides for enhanced SRAM cell performance and yield, and hence facilitates reductions in cell area and operating voltage. It also enables a notchless 6-T SRAM cell design which is advantageous for improved lithographic printability and either smaller area or lower standby power, and is projected to achieve 6-sigma cell yields at operating voltages down to ~0.8 V.