Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect

Abstract

In this paper the analysis of SNM, RNM, WNM and static power variation with width of access, load and driver have been carried out for nanoscale FinFET based SRAM cell. FinFET based SRAM design has been proposed as an alternative solution to the bulk devices. It can be inferred from the results that with increase in the width of driver FinFET, the high SNM reduces and low SNM increases. This is due the fact that the leakage current is considerably reduced due to increased control of the FinFET device structure, resulting relatively in highIon/Ioffratio. Further, the effect of process variation on the SRAM cell performance was analyzed using Monte Carlo simulation on HSPICE. The Monte Carlo simulation results for RNM and WNM to quantify the effect of process variation arising due to variation in FinFET's widths. The simulation was carried out for 1000 values, assuming 3σ equal to 10% of the mean value. Two structures of the FinFET viz. the standard PTM model and an underlapped FinFET have been also used for the simulations. It was identified that while the relative levels of the noise margins were lower for the underlapped case, the standard deviation was considerably lower too. In this work we also analyze the effect of temperature on noise margins and static power for FinFET based SRAM cell. FinFET is suitable for future nanoscale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current.