Performance Of Low Noise Amplifier Research Articles

The Design of the Weak Signal Conditioning Circuit

This paper describes the design of weak signal conditioning circuit. The amplitude of weak signal is very small and can easily be submerged by the noise, so when we choose the component for the circuit, in order to diminish the noise of the conditioning circuit, we choose a kind of low-noise operational amplifier for conditioning the signal. This circuit is applicable to the slow-varying direct current signal, even when the amplitude of the signal is dozens of microvolt, it still can work as normal.

A V-Band Common-Source Low Noise Amplifier in a 0.13.MU.m RF CMOS Technology and the Effect of Dummy Fills

In this work, a V-band low noise amplifier (LNA) is developed in a commercial 0.13µm RFCMOS technology. Common-source (CS) topology, known to show a better noise performance than the cascode topology, was adopted and 4-stage was employed to achieve a sufficient gain at the target frequency near the cutoff frequency fT. The measured gain was 18.6dB with VDD=1.2V and increased up to 20.2dB with VDD=1.8V at 66GHz. The measured NF showed a minimum value of 7.0dB at 62GHz. DC power consumption was 24mW with VDD=1.2V. The size of the fabricated circuit is as compact as 0.45mm × 0.69mm. This work was further extended to investigate the effect of dummy fills on LNA performance. An identical LNA, except for the dummy fills formed very close to (and under) the metal lines of spiral inductors and interconnects, was also fabricated and compared with the standard LNA. A peak gain degradation of 3.6dB and average NF degradation of 1.3dB were observed, which can be ascribed to the increased mismatch and line loss due to the dummy fills.

Effect of collector bias current on the linearity of common-emitter BJT amplifiers

Using a Volterra series, an explicit formula is derived for the connection between input 3rd-order intercept point and collector bias current (ICQ) in a common-emitter bipolar junction transistor amplifier. The analysis indicates that the larger ICQ is, the more linear the amplifier is. Furthermore, this has been verified by experiment. This study also integrates a method called dynamic bias current for expanding the dynamic range of an LNA (low noise amplifier) as an application of the analysis result obtained above. IMR3 (3rd-order intermodulation rate) is applied to evaluate the LNA's performance with and without adopting this method in this study.

Novel analysis and optimization of gm-boosted common-gate UWB LNA

This paper focuses on the design optimization of gm-boosted common gate (CG) CMOS low-noise amplifier (LNA) for ultra-wideband (UWB) wireless technology. In this regard, a detailed novel analysis of the UWB gm-boosted CG amplifier topology is presented, which includes the finite gds (=1/reds) effects. For UWB systems, signal-to-noise ratio (SNR) can be defined as the matched filter bound (MFB). Using this definition, the noise performance of the UWB CG LNA in the presence of the gm-boosting gain and the input noise-matching network are analyzed. It is found that the optimal noise factor of the UWB LNA collapses to the published narrowband gm-boosted CG LNA noise factor when an assumption of narrowband is applied. It is also proved that the noise performance of the gm-boosted UWB CG LNA is independent of the bandwidth of the input UWB signal. A new technique is presented for the design of optimal noise-matching network using passive components at the input of the UWB CG LNA. In this regard, role of the gm-boosting stage and its effect on the SNR and the gain of the overall system are analyzed, and, in addition, its non-idealities are simulated in detail.

A New Circuit Topology for the Realization of Very Low Noise, High Stability Voltage Sources

A new topology for the realization of high-stability very low noise voltage references is presented. The topology relies on a self-biasing circuit configuration based on a low-noise operational amplifier (OA). The series connection of a number of forward-biased low-noise diodes is used as an internal reference for generating any desired output voltage. The circuit may include a temperature stabilization system for obtaining very high stability coupled to very low noise. As an example, a 5-V reference with an output power spectral density of as low as 22 nV√Hz at 100 mHz, 7 nV√Hz at 1 Hz, and less than 6 nV√Hz for frequencies larger than 10 Hz can be obtained with a temperature stability better than 15 V/°C (less than 3 ppm/°C).

Electro-thermal stress effect on InGaP/GaAs heterojunction bipolar low-noise amplifier performance

Abstract This paper investigates the electro-thermal stress-induced performance degradation of a cascode low-noise amplifier built using advanced InGaP/GaAs heterojunction bipolar transistors. Changes in device characteristics due to the electro-thermal stress are examined experimentally. SPICE Gummel-Poon model parameters extracted from the pre- and post-stress HBT measurement data are then used in Cadence SpectreRF simulator to study the impact of the electro-thermal stress on the InGaP/GaAs LNA’s RF performance.

Low-Noise Active-RC Allpole Filters Using Optimized Biquads

In this paper it is shown that active-RC filters can be designed to have low-sensitivity to passive components and at the same time possess low output thermal noise. The design procedure of low-noise and low-sensitivity, positive-feedback, second- and third-order low-pass allpole filters, using impedance tapering, has already been published. The noise analysis in this paper was extended to the high-pass and band-pass filters and those with negative-feedback. The optimum designs, regarding both noise and sensitivity of most useful filter sections were summarized in the table form (as a cookbook) and demonstrated on examples. The classical methods were used to determine output noise spectral density and total rms output noise of filters. It was found that low-sensitivity filters with minimum noise have reduced resistance levels, low Q-factors, low-noise operational amplifiers and use impedance tapering design.

Component Tolerance Effect on Ultra-Wideband Low-Noise Amplifier Performance

A study of the component tolerances on an ultra-wideband (UWB) low-noise amplifier designed on a conventional printed circuit board is presented in this paper. The low-noise amplifier design employs dual-section input and output microstrip matching networks for wideband operation with a low noise figure and a flat power gain. First, the effect of passive component and manufacturing process tolerances on the low-noise amplifier performance is theoretically studied by means of sensitivity analyses. Second, simulation and measurement results are presented for verification of the analytical results. It is shown that, compared with a lumped matching network design, a microstrip matching network design significantly reduces the UWB low-noise amplifier sensitivity to component tolerances.

A Design Technique for Power Constrained CMOS Low-Noise Amplifier Dedicated to Wireless Sensor Networks

n wireless sensor network applications, autonomy is a critical feature. So, a new design method under power consumption constraint, dedicated to inductively degenerated Low-Noise Amplifier, is proposed in this article. A detailed analysis of power consumption, gain, noise and linearity performances of this topology is performed. The simulation results using MATLAB show the impact of each MOSFET dimensions into Low-Noise Amplifier performances. Based on these results, a new method to design Low-Noise Amplifier is proposed using an example. A 868-MHz Low-Noise Amplifier is then designed in CMOS 0.35 μm technology to validate our method. Considering the literature, measurement results show good characteristics: 13 dB gain, 1.5 dB Noise Figure with an ultra low-power consumption of 6.7 mW at supply voltage of 2 V.

Simulation of noise figure of nonlinear amplifiers using the orthogonalization of the nonlinear model

A simulation procedure of noise figure (NF) of nonlinear amplifiers is developed. NF is defined in terms of the effective signal-to-noise ratio (SNR) at the output of a nonlinear amplifier. The effective output SNR when the input consists of a communication signal plus Gaussian noise is evaluated through the identification of the effective output noise and nonlinear distortion power using the orthogonalization of the nonlinear model. The approach is useful for the assessment of noise performance of low-noise amplifiers in wireless systems. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE 2009.

Design procedure for optimizing CMOS low noise operational amplifiers

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier. The design procedure focuses on the noise performance, which is the key requirement for low noise operational amplifiers. Based on the noise level and other specifications such as bandwidth, signal swing, slew rate, and power consumption, the device sizes and the biasing conditions are derived. In order to verify the proposed design procedure, a three-stage operational amplifier has been designed. The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.

Design of an adaptive LNA for hand‐held devices in a 1‐V 90‐nm standard RF CMOS technology: From circuit analysis to layout

This paper deals the design of a reconfigurable Low‐Noise Amplifier (LNA) for the next generation of wireless hand‐held devices by using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing the fulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such that the mathematical design flow is simple as well as suitable for hand‐work in both laboratory and classroom. The circuit under analysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two‐stage topology including inductive‐source degeneration, MOS-varactor based tuning networks, and programmable bias currents. This proposal, with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications; the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b‐g). In order to evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA features NF<1.77dB, S21>16dB, S11<-5.5dB, S22<-5.5 dB and IIP3>-3.3 dBm over the 1.85-2.48 GHz band. For all the standards under study the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1‐V. The layout of the reconfigurable LNA occupies an area of 1.8mm2.

A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 mum CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under -9 dB in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 mm2.

A 0.5 V Area-Efficient Transformer Folded-Cascode CMOS Low-Noise Amplifier

A 0.5 V transformer folded-cascode CMOS low-noise amplifier (LNA) is presented. The chip area of the LNA was reduced by coupling the internal inductor with the load inductor, and the effects of the magnetic coupling between these inductors were analyzed. The magnetic coupling reduces the resonance frequency of the input matching network, the peak frequency and magnitude of the gain, and the noise contributions from the common-gate stage to the LNA. A partially-coupled transformer with low magnetic coupling has a small effect on the LNA performance. The LNA with this transformer, fabricated in a 90 nm digital CMOS process, achieved an S 11 of -14 dB, NF of 3.9 dB, and voltage gain of 16.8 dB at 4.7 GHz with a power consumption of 1.0 mW at a 0.5 V supply. The chip area of the proposed LNA was 25% smaller than that of the conventional folded-cascode LNA.

A Simple Figure of Merit of RF MOSFET for Low-Noise Amplifier Design

In this letter, it is proposed that g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> , which has been used as the figure of merit (FoM) of MOSFETs for analog amplifiers, can also be used as the RF MOSFET FoM for optimizing low-noise amplifier (LNA) performance. From a simple small-signal equivalent circuit, signal gain, noise figure, and power consumption equations are derived analytically and verified with the measurement results of the fabricated LNA. The proposed g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> predicts the optimal bias point for the maximum LNA performance.

Design and Study on Power Supply for Giant Magnetostrictive Accurate-Motion Actuator

The architecture and operation theory of Giant Magnetostrictive Accurate-motion Actuator have been introduced. After analysing the driving characteristic of giant magnetostrictive material and requirement of driving power, a design method of wide range and high precision NC constant-current source has been put out. The output circuit is composed of serial 12-bit DACs Max531, low-noise high-speed precision operational amplifiers OP27 and driving circuit. It provides current from 0 to 2.048A with 0.5mA step value. Two fully differential input channels 16-bit, sigma-delta ADCs AD7705 collects output current in feedback loop. Current ripple is controlled under 0.25mA through using homemade high-performance linear power. The result shows that the driving power with characteristic of high stability and fast response meets the needs of driving of Giant Magnetostrictive Accurate-motion.

Variation tolerant design methods for wideband low noise amplifiers

In this paper, we develop design techniques for reducing the impact of manufacturing variations on wideband low noise amplifiers (LNA). Utilizing an efficient modeling and circuit optimization method, we investigate the sensitivity of LNA performance metrics to process variations and determine that the input impedance matching is particularly sensitive to perturbations in component values. To mitigate the impact of process variations on the input impedance matching, we add additional circuit elements and tunable capacitors to dynamically compensate for manufacturing variations after fabrication. The results indicate that the proposed design techniques can increase manufacturing yield by up to one order of magnitude for input impedance matching with only a 14% increase in noise figure.

Optimisation of Gate-Drain/Source Overlap in 90 nm NMOSFETs for Low Noise Amplifier Performance

The effect of gate-drain/source overlap (L ov ) on LNA performance has been studied, in 90 nm NMOSFETs using process, device and mixed mode simulations. In order to have a fair comparison, the off-state leakage current (I OFF ) of MOSFETs is kept constant by adjusting the pocket halo dose as a function of varying L ov . A basic LNA circuit with two transistors in cascode arrangement is constructed and the input impedance, gain and noise-figure have been used as performance metrics. It has been shown that 'control over L ov ' allows us to get better power and noise performance from the LNA i.e., it allows us to get minimum noise figure (NF) and maximum gain from the LNA. To get the better noise performance and gain, L ov in the range of 0-10 nm is recommended.

Receiver Front-End Circuits for Future Generations of Wireless Communications

In this paper, new receiver concepts and CMOS circuits for future wireless communications applications are introduced. The concepts derived are applied to a few classes of wireless communications standards that are broad-band at radio frequencies and/or require a broad-band baseband circuitry. Multimode multiband operation and adaptivity as key requirements for future generation receivers are highlighted throughout the paper. The tradeoffs between power consumption, noise figure and linearity performance of low-noise amplifiers, mixers, and intermediate frequency filters are considered too.

Design techniques for reducing the impact of component variations on narrow-band low noise amplifiers

Given the increasing demand for integrated wireless systems in system-on-chip technology, narrow-band low noise amplifier (LNA) designs must be robust against variations in device parameters and passive component values to improve manufacturing yield for high volume applications. In this paper, we develop two design techniques for reducing the impact of component variations on narrow-band LNA performance. The results demonstrate that by increasing the bandwidth of the narrow-band LNA and applying more conservative design constraints, we can mitigate the reliability implications of process variations on impedance matching, gain, and power consumption.