Design of an adaptive LNA for hand‐held devices in a 1‐V 90‐nm standard RF CMOS technology: From circuit analysis to layout

Abstract

This paper deals the design of a reconfigurable Low‐Noise Amplifier (LNA) for the next generation of wireless hand‐held devices by using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing the fulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such that the mathematical design flow is simple as well as suitable for hand‐work in both laboratory and classroom. The circuit under analysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two‐stage topology including inductive‐source degeneration, MOS-varactor based tuning networks, and programmable bias currents. This proposal, with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications; the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b‐g). In order to evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA features NF<1.77dB, S21>16dB, S11<-5.5dB, S22<-5.5 dB and IIP3>-3.3 dBm over the 1.85-2.48 GHz band. For all the standards under study the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1‐V. The layout of the reconfigurable LNA occupies an area of 1.8mm2.