Performance Of Digital Circuits Research Articles

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time (t). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre-and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre-and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in Eldo SPICE environment with 65 nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

Performance Analysis of 8-Bit Carry Select Adder

In this study, we evaluated the performance of an 8-bit carry-select adder (CSA) implemented through transmission gates for various metrics such as speed and area. Adders are an important part of digital computer systems and are used to perform additional operations. CSA is a well-known adder type known for its fast performance. Our results suggest that CSA implemented using transmission gates may improve the performance of digital circuits by achieving faster performance due to the low resistance and fast switching properties of these gates. In addition, we also analyzed the area utilization of CSA by measuring the number of transistors in the synthesized design. The integration of transmission gates into the CSA can affect area characteristics and our analysis provides insight into the design's area efficiency. CSA was developed in this study using transmission gate technology along with MTCMOS D-latch to achieve superior performance compared to previous studies. Simulations were performed using 250nm CMOS technology from Tanner and Mentor Graphics. His CSA implementation with transmission gate logic significantly reduced transistor count by 58.85% compared to his conventional CSA. This approach was chosen for its better results and improved overall performance.

NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hoc resistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale.

Silicon-based optoelectronics for general-purpose matrix computation: a review

Conventional electronic processors, which are the mainstream and almost invincible hardware for computation, are approaching their limits in both computational power and energy efficiency, especially in large-scale matrix computation. By combining electronic, photonic, and optoelectronic devices and circuits together, silicon-based optoelectronic matrix computation has been demonstrating great capabilities and feasibilities. Matrix computation is one of the few general-purpose computations that have the potential to exceed the computation performance of digital logic circuits in energy efficiency, computational power, and latency. Moreover, electronic processors also suffer from the tremendous energy consumption of the digital transceiver circuits during high-capacity data interconnections. We review the recent progress in photonic matrix computation, including matrix-vector multiplication, convolution, and multiply–accumulate operations in artificial neural networks, quantum information processing, combinatorial optimization, and compressed sensing, with particular attention paid to energy consumption. We also summarize the advantages of silicon-based optoelectronic matrix computation in data interconnections and photonic-electronic integration over conventional optical computing processors. Looking toward the future of silicon-based optoelectronic matrix computations, we believe that silicon-based optoelectronics is a promising and comprehensive platform for disruptively improving general-purpose matrix computation performance in the post-Moore’s law era.

Digital Circuit Performance Evaluation of Parallel Gated Junctionless Field Effect Transistor

This paper reports the modeling and performance enhancement of complementary metal-oxide-semiconductor (CMOS) inverters using parallel-gated junctionless field-effect transistors (PGJLFET). A mathematical model for different parameters, namely, low and high input voltage, low and high output voltage, noise margin, rise time, fall time, propagation delay, and power dissipation of the inverter circuit was established. To establish the model for various parameters, potential models at the source-channel boundary and the potential at the drain-channel boundary are considered. The variations in the voltage transfer characteristics of the output current with respect to the input voltage and the power dissipation with respect to the input voltage for steady-state conditions and transient states were investigated for different gate dielectrics, gap lengths, and gate oxide thicknesses. The models were validated by comparing them with technology computer-aided design (TCAD) simulation results. The noise margin, rise time, fall time, and propagation delay of the PGJLFET-based inverter are estimated and compared with those of a conventional junctionless transistor. It has been observed that the PGJLFET exhibits an improvement in the noise margin and propagation delay compared with conventional junctionless transistors.

Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation

Approximate computing is a promising technique to elevate the performance of digital circuits at the cost of reduced accuracy in numerous error-resilient applications. Multipliers play a key role in many of these applications. In this brief, we propose a truncation based Booth multiplier with a compensation circuit generated by selective modifications in k-map to circumvent the carry appearing from the truncated part. By judicious mapping, hardware pruning and output error reduction is achieved simultaneously. In the quest of power and accuracy trade-off, Truncated and Approximate Carry based Booth Multipliers (TACBM) are proposed with a range of designs based on truncation factor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${w}$ </tex-math></inline-formula> . When compared with the state-of-the-art multipliers, TACBM outperforms in terms of accuracy and Area-Power savings. TACBM( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${w}=10$ </tex-math></inline-formula> ) provides with 0.02% MRED and 23% reduction in Area-Power product compared to exact Booth multiplier. The multipliers are evaluated using image blending and Multilayer perceptron (MLP) neural network and a high value of accuracy (95.63%) for MLP is achieved.

Fully-integrated DCDC buck converter based on PID algorithm

With the continuous development of power supply technology, the application of power management chips becomes more extensive, and the requirements for fully integrated power management chips are getting higher. This paper designs a buck converter with a fully integrated digital control circuit and power circuit with an output voltage of 2V. In voltage mode, digital pulse width modulation (DPWM) technology and PID algorithm are used, and a digital closed-loop control buck circuit system is designed by cadence tools. The performance of analog and digital closed-loop control circuits is compared at the same buck power stage. Under rated load conditions, the lock-up time of the digital control buck circuit is 826us, the output voltage ripple is 14.75mV, the response time of load sudden change at light load is about 900us, and the response time of load sudden change at heavy load is about 2ms.

Cylindrical SOI Schottky Barrier MOSFET with High Linearity and Low Static Power for Digital and Analog Circuits Application

Non-linearity and static power consumption are major challenges in the designing of digital and analog circuits. To improve the performance of digital and analog circuits, a proper selection of MOSFET device architecture is essential. The MOSFET device architecture with low static power dissipation and high linearity results in improves overall performance at the circuit level. In this work, a detailed analysis of cylindrical Silicon-on-Insulator (SOI) Schottky Barrier (SB) MOSFET is done for analog and digital circuit applications. The analog device parameters and device non-linearity parameters for SOI SB MOSFET are extracted and compared with SB MOSFET and Dielectric Pocket (DP) SB MOSFET. The SOI SB MOSFET shows an improvement of 6.905% in output conductance (gds), 130.513% in early voltage (Vea), 240.74% in transconductance generation factor (TGF), 35.901% in transconductance frequency product (TFP), 23.529% in the gain-bandwidth product (GBWP), 25.542% in voltage gain (Av), 130.968% in gain frequency product (GFP), and 179.964% in gain transconductance frequency product (GTFP). Third-order extrapolated voltage (VIP3), third-order extrapolated power (IIP3), and extrapolated intermodulation power (IMD3) have also improved in comparison to SB MOSFET. The Atlas 3-D device simulation tool is used for numerical simulations.

The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

Capacitance model for nanowire gate-all-around tunneling field-effect-transistors

The nanowire gate-all-around (GAA) structures with the nearly ultimate channel electrostatic integrity of the gate field can exhibit the best immunity to the short channel effect and drain-induced barrier lowering. Moreover, owing to the enhanced control efficiency of gate over the tunneling junction, the GAA-TFET also gives improved subthreshold swing and on-state current. Despite the excellent device performance, an accurate model is very significant for the practical application. Compared with the numerical methods which are usually time consuming and computationally inefficient, an analytical model could accelerate the device investigation and circuit design process. Even though some tunneling current models have already been reported for nanowire tunneling field-effect-transistors (TFETs), the model of the terminal capacitance is still an issue for nanowire TFETs. The capacitance is of great significance for the transient simulation. In this paper, a physical and analytical potential model considering both the source depletion region and the channel mobile charges, is developed for the GAA-TFETs. The results from the model are verified with the numerical simulations, and the excellent agreement between the two results indicates the validation of the proposed model. Based on the potential model, the terminal charge model and the capacitance model are further developed and also verified by the numerical simulations. The main inflection and variation of the terminal charges and capacitances with the biases can be predicted by our model. Besides, both the model results and the numerical simulations both demonstrate that the gate charge is dominated mainly by the drain charges and the contribution of the source charges can be almost neglected. This also leads to the very small gate-source capacitance and very large Miller capacitance in the TFET device. This will be detrimental to the performance of TFET-based digital circuits but can be mitigated with the hetero-oxide gate structure. The second order effects, such as the quantum confinement and traps, are ignored in this paper and can be taken into the core model in the future work. It should also be noted that there is no iterative process involved during the model derivation, thus the developed model can be easily applied to the widely used SPICE platform and will be useful in designing and investigating the GAA-TFET based circuits.

Модификация алгоритма Pathfinder для этапа трассировки межсоединений ПЛИС

One of the main advantages of FPGA and CPLD is the high development speed; therefore, the importance of effective computer-aided design tools for modern microcircuits of these classes cannot be overestimated. Placement and routing are the most time-consuming stages of FPGA/CPLD design flow. The quality of results of these stages is crucial to the final perfor-mance of custom digital circuits implemented on FPGA/CPLD. The paper discusses an approach to accelerating the routing stage within the layout synthesis flow for FPGA/CPLD by introducing a few algorithmic improvements to a routing procedure. The basic routing algorithm under study is a modified Pathfinder for a mixed routing resource graph. Pathfinder is a well-known negotiation-based routing algorithm that works on the principle of iteratively eliminating congestions of chip routing resources. For experiments, the sets of test digital circuits ISCAS'85, ISCAS'89, LGSynth'89 and several custom industrial projects were used. The impact of the proposed algorithmic improvements was analyzed using four FPGA/CPLD architectures. It has been established that due to the improvements of the algorithm proposed in the paper, the average reduction in routing time was from 1.3 to 2.6 times, depending on the FPGA/CPLD architecture, with no significant negative effect on the timing characteristics of the designed circuits.

Non-Volatile Wideband Frequency Tuning of a Ring-Oscillator by Charge Trapping in High-k Gate Dielectric in 22nm CMOS

Process and parametric variation negatively impact the performance and yield of analog and digital circuits in advanced nodes. To alleviate this effect, we propose a technique to electrically adjust the threshold voltage of CMOS transistors in a post-fabrication setting in a non-volatile manner. This technique, which relies on self-heating assisted trapping of charge in high-k gate dielectric (e.g. HfOx) used in advanced CMOS nodes, does not require any extra fabrication step. In this letter, we use charge trapping for wideband non-volatile frequency tuning of a ring oscillator. We have demonstrated that the frequency of the ring oscillator can shift from 2075MHz to 1746MHz, when a supply voltage of 0.8V is used. This work serves as a foundation for non-volatile tuning, reconfiguration, and obfuscation of chips and IP blocks. The chip was fabricated in GlobalFoundries 22nm Fully-Depleted Silicon-on-Insulator (FDSOI) CMOS process.

Engineering substrate doping in bulk planar junctionless transistor: Scalability and variability study

In this work two dimensional sentaurus simulations are used to study the impact of substrate doping on scalability and the variability of the bulk planar junctionless transistor (BPJLT). The results shows that, although increasing substrate doping density in BPJLT reduces the off-state current, subthreshold slope and the drain induced barrier lowering, the on-state current of the device is almost constant. To improve digital logic circuit performance of nanoscale BPJLT, novel δ-layer BPJLT (δ-BPJLT) is being proposed by incorporating p-type δ- layer below the uniformly doped device layer containing source, channel and the drain regions of BPJLT. It has been found that, the δ-layer below the device layer leads to reduction in the off-state current, process induced variability and the short-channel effects of the BPJLT. This is mainly because of the screening effect due to δ-layer under the device layer which significantly reduces the variations induced because of random dopant fluctuations.

Sense Amplifier Half Buffer Based Ripple Carry Adder for IEEE 754 Standards

Addition is a specifically used indispensable computation used for most of the applications including digital systems and control systems. Adder is a primitive constituent used in the construction of digital IC; also it is an essential part of signal processing applications like DSP. The speed of an adder circuit holds a considerable influence on the total performance of digital circuits. The prime objective of this research is to design ripple carry adder using different asynchronous logics like Multithreshold null convention logic (MTNCL), Multi-threshold dual spacer dual rail delay insensitive logic (MTD3L) and proposed Sense amplifier half buffer logic (SAHB). SAHB is an asynchronous Quasi-Delay -Insensitive (QDI) method used to achieve significant functional speed of the circuit. The standard library cells (2-input AND/NAND, 2-input OR/NOR, 2-input XOR/XNOR) are designed using proposed SAHB logic to design an 8- bit Ripple Carry Adder circuit. The proposed SAHB logic design provides the solution of minimum delay with improved speed compared to the existing logic design techniques. The asynchronous logics are designed using mentor graphics tool with 130nm technology. Various performances attributes like power dissipation, delay and energy are tabulated and compared with existing logics.

Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications

This paper proposes a 2-D analytical model developed for Double Gate Junctionless Transistor with a SiO2/HfO2 stacked oxide structure. The model is solved by Poisson’s equation using the variable separation method. The proposed model gives analytical expressions for electrostatic potential distribution, threshold voltage and drain current with the effects of depletion regions at source/drain side. Furthermore, the potential and drain current models are used to evaluate the Short Channel Effects (SCEs) of the proposed device. The electrical characteristics and SCEs are analyzed by different possible definitions of channel length, silicon thickness, equivalent oxide thickness, and depletion length variations. The developed model results are validated through comparison with Sentarus TCAD simulator results. In addition, the proposed device is also studied for the digital circuit performance of CMOS inverter circuit by the voltage transfer characteristics, transient analysis, and AC small signal analysis.

Investigation of Hot-Carrier Degradation in 0.18-$\mu$ m MOSFETs for the Evaluation of Device Lifetime and Digital Circuit Performance

In this work, we investigate the hot-carrier reliability in $0.18{\mu}\text{m}$ MOSFET technology that is being extensively employed in various analog/digital applications. Hot-carrier degradation in MOSFETs is known to follow power-law relation where the time exponent of the degradation curve can be utilized to quantify the device ageing. Here, we examine the dependency of time power-law exponent on different gate stress bias to determine the physical mechanism responsible for device degradation. Extensive consideration is given to the maximum impact ionization condition Vgs = Vds/2 and maximum hot-electron injection condition Vgs = Vds . Time evolution of degradation curve depicts changing slope with increasing stress duration. This variation in time power-law exponent over different stress time intervals is an important indicator of changing degradation mechanism as the device ages. Since the operating conditions for a device directly relates to its targeted application, therefore DC lifetime prediction under the influence of different Vgs/Vds stress bias combinations is performed to determine the limiting case challenging the circuit integrity. Also, the impact of hot-carrier degradation on the circuit delay under the aforementioned stress conditions is evaluated for typical digital CMOS circuits. Effective switching current methodology is employed for the delay analysis in transistor stacks that comprise inverter, NAND, and NOR circuits to show the adverse effects of the damage caused by the hot-carriers.

A smart noise- and RTN-removal method for parameter extraction of CMOS aging compact models

In modern nanometer-scale CMOS technologies, time-zero and time-dependent variability (TDV) effects, the latter coming from aging mechanisms like Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) or Random Telegraph Noise (RTN), have re-emerged as a serious threat affecting the performance of analog and digital integrated circuits. Variability induced by the aging phenomena can lead circuits to a progressive malfunction or failure. In order to understand the effects of the mentioned variability sources, a precise and sound statistical characterization and modeling of these effects should be done. Typically, transistor TDV characterization entails long, and typically prohibitive, testing times, as well as huge amounts of data, which are complex to post-process. In order to face these limitations, this work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔVth) related to oxide defects in nanometer CMOS transistors during aging tests. At the same time, the aging testing methodology significantly reduces testing times by parallelizing the stress. The method identifies the Vth drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.

A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction

A comprehensive simulation flow is demonstrated to assess the negative-bias temperature instability (NBTI) impact on the performance and power of digital logic circuits based on the 14-nm node FinFET technology. Fully calibrated technology computer-aided design simulations are used to determine the preaged and postaged device characteristics; the results are used for calibrating the BSIM-CMG compact model. Standard cell libraries are characterized next, by only threshold voltage shift ( $\Delta {V}_{\text {T}}$ ) and by both $\Delta {V}_{\text {T}}$ and subthreshold slope shift ( $\Delta $ SS). Various benchmark circuits are synthesized and analyzed, and their timing degradation is compared to ring oscillator results. The consequence of ignoring $\Delta $ SS on OFF current and static power ( ${P}_{\text {static}}$ ) is estimated.

Analog and digital signal processing method using multi-time-over-threshold and FPGA for PET.

The goal of this study was to develop an analog and digital signal processing method using multi-time-over-threshold (MTOT) and field programmable gate arrays (FPGAs) to extract PET event information by using the internal clock of FPGA (~350 MHz), without ADC and TDC. The PET detector modules were composed of a 4 × 4 matrix of 3 × 3 × 20 mm3 LYSO and 4 × 4 SiPM array. Output charge signals of PET detector modules were amplified and fed into four comparators to generate trigger signals. The energy of the detected gamma ray was calculated by integrating the digitized pulse and the arrival time was determined from the time stamp of the lowest trigger signal by FPGA. The data packet containing energy, time, and position information was stored in list mode on the host computer. The performance of analog and digital signal processing circuits using MTOT method and FPGA was evaluated by measuring energy and time resolution of the proposed method and the values were 19% and 900 ps, respectively. This study demonstrated that the proposed MTOT method consisting of only FPGA without ADC and TDC could provide a simple and cost-effective analog and digital signal processing system for PET.

Bandgap-dependent onset behavior of output characteristics in line-tunneling field-effect transistors

The onset behavior of output characteristics in tunnel field-effect transistors (TFETs) importantly determines the performance of digital TFET-based circuits. In this paper, we analytically and numerically examine the dependence of the onset behavior of output characteristics on the bandgap of semiconductors in line-tunneling TFETs. The qualitative and quantitative analyses show that the output onset behavior in line-tunneling TFETs strongly depends on the bandgap because the roles of two factors, including the incident electron number and tunneling probability, in determining the variation of tunneling current under increasing drain voltage change oppositely when varying the bandgap. Particularly, the superlinear onset in line-tunneling TFETs can be effectively suppressed to reduce the saturation drain voltage by using low-bandgap semiconductors. Together with the advantages in on-current and subthreshold swing as shown previously, the significant superiority in output characteristic makes the use of low-bandgap materials to be an efficient approach for simultaneously enhancing the device and circuit performances of advanced line-tunneling TFETs.