Abstract

Addition is a specifically used indispensable computation used for most of the applications including digital systems and control systems. Adder is a primitive constituent used in the construction of digital IC; also it is an essential part of signal processing applications like DSP. The speed of an adder circuit holds a considerable influence on the total performance of digital circuits. The prime objective of this research is to design ripple carry adder using different asynchronous logics like Multithreshold null convention logic (MTNCL), Multi-threshold dual spacer dual rail delay insensitive logic (MTD3L) and proposed Sense amplifier half buffer logic (SAHB). SAHB is an asynchronous Quasi-Delay -Insensitive (QDI) method used to achieve significant functional speed of the circuit. The standard library cells (2-input AND/NAND, 2-input OR/NOR, 2-input XOR/XNOR) are designed using proposed SAHB logic to design an 8- bit Ripple Carry Adder circuit. The proposed SAHB logic design provides the solution of minimum delay with improved speed compared to the existing logic design techniques. The asynchronous logics are designed using mentor graphics tool with 130nm technology. Various performances attributes like power dissipation, delay and energy are tabulated and compared with existing logics.

Highlights

  • Earlier days, the principle challenge of VLSI designer is to reduce the area of chip [1, 2]

  • The enormous advancement in technology allows the designer to aim for low power, portable and high speed digital circuits [3, 4, 9]

  • The performance of digital system depends upon speed and accuracy of an adder circuit

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Summary

Introduction

The principle challenge of VLSI designer is to reduce the area of chip [1, 2]. Arithmetic logic unit (ALU) requires an adder circuit for the purpose of addition and multiplication. Adders happen to be a vital hardware unit for the dynamic realization of ALU. They are widely used in various arithmetic and other kinds of applications especially in some parts of processor. Adder is a fundamental circuit used in digital arithmetic to perform addition of two N bit numbers. It is designed with the help of asynchronous (clock less) techniques due to its major advantages like less power consumption, lower interference due to Electro-Magnetic radiation (EMI) and high robustness correlated to the synchronous (clocked) design

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