Performance Of Carbon Nanotube Field-effect Transistors Research Articles

Metallization considerations for carbon nanotube device optimization

As a one-dimensional structure with atomically thin sidewalls, charge transport in carbon nanotubes can be regarded as a surface phenomenon. As such, perturbations from the surrounding environment can have a dramatic impact on transport and consequently on the device behavior of carbon nanotube field-effect transistors (CNTFETs). Importantly, this includes effects from device fabrication processes like contact metallization. With this as motivation, several aspects of contact metallization are investigated herein. First, it is found that ON current in n-type CNTFETs is enhanced to the level of p-type CNTFETs through the utilization of titanium as an adhesion layer, a result of improved wetting. Effects of different metallization techniques, namely, thermal and electron-beam evaporation, are also explored in p-type devices using titanium/palladium/gold contacts. It is found that thermal metallization consistently produces devices with higher ON current. In-depth analysis of the transfer characteristics reveals that this is due to radiation effects encountered during electron-beam processing, resulting in channel scattering and a decreased transconductance in the devices. This effect is particularly severe upon gold processing, and attempts to heal this device degradation through annealing proved unsuccessful. All studies presented here are conducted through the analysis of a large number of nanotube devices, giving a degree of confidence to the average results. Additionally, only device parameters that can be directly extracted from the transfer characteristics are analyzed. Assumptions including nanotube diameter, capacitance, and nanotube number per device are not made. Results from this study provide recommendations for optimizing CNTFET performance as it relates to contact metallization.

Analysis of CNTFET Performance in Sequential Device Using Shift Register for Low Power Applications

Nanotechnology has touched the post silicon era where the MOSFET has touched its least scaling value according to Moore’s law. Further lowering in the technology nodes had bring out Short channel effects that are reflected in reliability issues to electronic components which we could visualize in our day today activities. The alternative and the best replacement for CMOS technology is Carbon Nano Tube Field Effect Transistors (CNTFET). These Carbon nanotubes because of their distinctive nature in structural, electrical and mechanical properties will be the building blocks for future Nano electronics. This work focused on design and analysis of Sequential logic devices using CNTFET and comparative analysis with CMOS performance. For Sequential device analysis, we considered Shift register as these forms the basic building block of memory devices. These devices helps in storage or in transfer of binary data. For designing Shift registers we proposed Pulsed latches rather than the regular flip-flops as they consume more power. The design has been implemented in both CNTFET and CMOS technologies for 32nm technology node. The comparative findings show that our suggested job has better Power, Delay and Power Delay Product performance.

LOW LEAKAGE CHARGE RECYCLING TECHNIQUE FOR POWER MINIMIZATION IN CNTFET CIRCUITS

Carbon Nanotube Field Effect Transistor (CNTFET) is one of the most promising candidates in the near future for digital design due to its better electrostatics and higher mobility characteristics. Parameters that determine the CNTFET performance are the number of tubes, pitch, diameter and oxide thickness. In this paper, a power gating design methodology to realise low power CNTFET digital circuits even under device parameter changes is presented. Investigation about the effect of different CNTFET parameters on dynamic and standby power is carried out. Simulation results reveal that the power gated circuits suppress a maximum of about 67% dynamic power and 59% standby power compared to conventional circuits.

Comparative Analysis of Control Coefficients on the Performance of CNTFET Under Different Parameters

This paper deals with the performance of both gate and drain control coefficients to analyze the behavior of carbon nanotube field effect transistors (CNTFETs) under ballistic conditions and based on the change of different parameter value, such as oxide thickness of structure and temperature variation. A thorough study of both gate and drain control coefficient effects on the performance of CNTFETs has been conducted under different temperature and oxide layers and the output of the device has been analyzed through different parameters. Higher values of control coefficient help to attain larger transconductance by the increasing temperatures. For a fixed value of control coefficient, 4[Formula: see text]nm thickness of oxide has a transconductance of [Formula: see text] 4.5 [Formula: see text] 10[Formula: see text] S/m. Smaller oxide layer thickness has higher slope of increment in transconductance value. ON-state current to leakage current ratio shows a steady state response toward increment of gate control coefficient. Also, increment of oxide thickness has an adverse effect on current ratio, while a linear decay of current ratio is observed with the increased value of drain controlled one. Drain-induced battery lowering (DIBL) effect decreases with the value of gate control one and increases with the drain control coefficient. In this way, the optimum value for both the control coefficients has to be considered in order to perform well.

Channel and Gate Workfunction-Engineered CNTFETs for Low-Power and High-Speed Logic and Memory Applications

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green’s functions (NEGF) solved self - consistently with Poisson’s equations. It is revealed that hetero -material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ФSUBM1/SUB/ФSUBM2/SUB have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part II: Extrinsic Elements, Performance Assessment, and Design Optimization

We present a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) including contact resistance, direct source-to-drain and band-to-band tunneling currents. The model captures the effects of dimensional scaling and performance degradations due to parasitic effects and is used to study the trade-offs between the drive current and leakage current of CNFETs according to the selection of CNT diameter, CNT density, contact length, and gate length for a target contacted gate pitch. We describe a co-optimization study of CNFET device parameters near the limits of scaling with physical insight, and project the CNFET performance at the 5-nm technology node with an estimated contacted gate pitch of 31 nm. Based on the analysis including parasitic resistance, capacitance, and tunneling leakage current, a CNT density of 180 CNTs/{\mu}m will enable CNFET technology to meet the ITRS target of drive current (1.33 mA/{\mu}m), which is within reach of modern experimental capabilities

High dielectric material dependence of carbon nanotube field effect transistor considering non‐ballistic conduction

As a result of this reported research, a simulation model to analyse the behaviour of carbon nanotube field effect transistors (CNTFETs) under non-ballistic conditions is explained and the effect of gate dielectric on the performance of CNTFETs has been explored in detail. For the first time, a thorough study of the combined non-ballistic effect on the performance of CNTFETs has been conducted and the output of the device has been analysed. It has been observed that a gate material with a high dielectric constant leads to higher on-state current and higher on and off state current ratio. In addition, the transconductance, total capacitance, charging energy, subthreshold swing (S), drain-induced barrier lowering (DIBL) and gain with respect to the dielectric constant have been observed and analysed. Transconductance and total capacitance increases by a significant amount, while charging energy and S decrease as the dielectric value increases. The DIBL and gain vary slightly as a higher value dielectric material is used as a gate. Furthermore, the results of this study have been plotted against previously reported ballistic outputs to provide a better perception of the deviation from ideal behaviour. At the same time, the outcomes of this analysis have been compared against some reported experimental values.

Effect of parametric variation on the performance of single wall carbon nanotube based field effect transistor

The effects of dielectric constant and gate insulator thickness on the performance of single wall carbon nanotube field effect transistors (CNTFETs) have been analyzed using a mathematical model based on FETToy simulator. Both the parameters are found to have significant effect on the device performance, particularly the on-current; while the on-current (ION) increases on scaling down the gate oxide thickness, the level of leakage current (IOFF) is not considerably affected. This is an advantage of CNTFET over conventional MOSFETs where the thickness of thin oxide layer causes drastic increase in gate leakage current. Our analysis results show that thinner gate oxide and larger CNT improve the performance of CNTFETs. Therefore, the performance of our simulated CNTFETs using this model has clear lead over those of conventional MOSFETs.

Improving non-suspended carbon nanotube FET performance by using an alumina protective layer

Fabrication of high-performance carbon nanotube field effect transistors (CNFETs) is an essential prerequisite for obtaining competitive CNFET-based gas sensors. In reality, the CNFET performance is heavily affected by lithography-induced resist residues on or around the nanotubes. These impurities aggravate the gate hysteresis and cause high electrical on-resistance of CNFETs. To address this problem, we present an approach using the atomic-layer-deposited alumina as a protective layer to prevent direct contact between carbon nanotubes (CNTs) and patterning resists. The alumina layer can be easily and completely removed from the CNTs prior to contact metallization. Based on the comparison of 491 devices, we find that the median on-resistance is reduced from 247kΩ to 134kΩ by using the alumina protective layer. Additionally, the median hysteresis width extracted from the CNFET transfer characteristics is narrowed dramatically from 2.2V to ∼0.5V. The simplicity of the presented process sequence allows for its easy integration into various fabrication processes involving CNTs.

Exploration of yttria films as gate dielectrics in sub-50 nm carbon nanotube field-effect transistors.

Thin yttria films were investigated for use as gate dielectrics in carbon nanotube field-effect transistors (CNTFETs) with the gate length scaled down to sub-50 nm size. The yttria film provided an omega-shaped gate dielectric with a low interface trap density, a low average sub-threshold swing of 74 mV per decade for both long and short CNTFETs, and a small drain-induced barrier lowering. It was also shown that the performance of CNTFETs increases with decreasing temperature, with an excellent sub-threshold swing of 22 mV per decade at liquid nitrogen temperatures. A method was developed to retrieve the interface trap density in CNTFETs and a low interface trap density of 5.2 × 10(6) cm(-1) was achieved, indicating the high electric quality of the yttria films.

Potential of carbon nanotube field effect transistors for analogue circuits

This Letter presents a detailed comparison of carbon nanotube field effect transistors (CNFETs) and metal oxide semiconductor field effect transistors (MOSFETs) with special focus on carbon nanotube FET's potential for implementing analogue circuits in the mm-wave and sub-terahertz range. The latest CNFET lithographic dimensions place it at-par with complementary metal oxide semiconductor in terms of current handling capability, whereas the forecasted improvement in the lithography enables the CNFETs to handle more than twice the current of MOSFETs. The comparison of RF parameters shows superior performance of CNFETs with a gm , f T and f max of 2.7, 2.6 and 4.5 times higher, respectively. MOSFET- and CNFET-based inverter, three-stage ring oscillator and LC oscillator have been designed and compared as well. The CNFET-based inverters are found to be ten times faster, the ring oscillator demonstrates three times higher oscillation frequency and CNFET-based LC oscillator also shows improved performance than its MOSFET counterpart.

Improvement on the electron transport efficiency of the carbon nanotube field effect transistor device by introducing heterogeneous-dual-metal-gate structure

To improve the carbon nanotube field effect transistor (CNTFET) device performance and enhance the electron transport efficiency of the device, a heterogeneous-dual-metal-gate (HDMG)-CNTFET is proposed. By appropriately modifying the transport model for single-metal-gate (SMG)-CNTFET, the electron transport properties of the HDMG-CNTFET device are investigated. The results indicate that the work function WGS of the metal gate near the source (S-gate) is fixed such that it is equal to that of the intrinsic CNT, and the work function WGd of the metal gate near the drain (D-gate) is selected to be smaller than WGS within a certain range, the electric field distribution can be optimised and the average electron velocity in the CNTFET channel can be significantly increased; at the same time, due to the electric potential modulation by the D-gate, the device has a lower threshold voltage. When the same operating voltage is applied, HDMG-CNTFET has a larger on-state current than SMG-CNTFT; and due to the shielding effect of the drain voltage variation by D-gate, the HDMG-CNTFET device exhibits good gate-control ability and can suppress the drain-induced barrier lower effect, hot electron effect and ambipolar conduction behavior compared with SMG-CNTFET. This study, by reasonably selecting the gate electrode work function of the HDMG-CNTFET, can effectively overcome the deficiency of existing research on improving the CNTFET performance at the expense of reducing the on-current, more importantly, can improve the electron transport efficiency, thereby improving the characteristic frequency and reducing the delay time of the device, which will be of benefit to CNTFET application in high-speed/high-frequency circuit.

Influence of Channel and Underlap Engineering on the High-Frequency and Switching Performance of CNTFETs

We have comprehensively studied the influence of the channel and underlap engineering on the switching and high-frequency performance of carbon nanotube field-effect transistors (CNTFETs). Various source/drain and channel-engineered CNTFETs have been investigated and optimized architectures have been concluded from simulations. Performance parameters such as switching time τ and cutoff frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> as well as ambipolarity and on/off ratio I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> have been calculated and optimized. New CNTFETs with staircase doping in the underlap region (SU-CNTFETs)] have been proposed and the optimized underlap length and doping level have been concluded. Adding this kind of underlaps to conventional CNTFETs improves f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , τ, and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> and limits the leakage current simultaneously. For the first time, laterally asymmetric channel CNTFETs with a realistic staircase doping (SLAC-CNTFETs) have been proposed. It is shown that SLAC-CNTFET has an improved RF and switching performance while maintaining a good I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> . The effect of single halo implantation on the aforementioned parameters has been calculated and it is revealed that it degrades the figures of merit. Detailed reasoning of the aforementioned characteristics has been discussed based on the gate and channel electric field distributions and the quantum capacitance. The impact of fringing field capacitances on f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> has been computed and shown that it is not negligible. Finally, our calculations for an individual CNTFET with metallic contacts showed that the Schottky barriers at the contacts deteriorate almost all the figures of merits except I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> .

An Effective Switching-Off Mechanism for High-Performance Carbon Nanotube Field-Effect Transistors

We report an effective switching-off mechanism for the fabrication of high-performance carbon nanotube field-effect transistors (CNTFETs) formed by ultra-purified single-walled carbon nanotubes (SWCNTs) with p-type Sb{sub 2}Te{sub 3} semiconductor as the source and drain contact material and a narrow platinum gate entirely defined inside the source and drain contact region. CNTFETs show drain-source current (I{sub DS}) as a function of drain-source voltage (V{sub DS}) and gate voltage (V{sub GS}) of similar characteristics to a p-channel junction field-effect transistor (JFET). CNTFETs are normally on, and they can be effectively switched off with applying a positive gate voltage. By localizing the gate action primarily on the SWCNTs, away from the source and drain contacts, we could clearly interpret the beneficial effect of semiconducting contacts on the performance of CNTFETs. The proposed device is novel and could be a solution to the switching-off problem in CNTFETs.

A process for high yield and high performance carbon nanotube field effect transistors

Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139 mV/dec, high transconductance of 1.27 μS, and high I on/ I off ratio of 10 6 can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future.

Comparative Investigation of the Effect of Oxygen Adsorbate and Electrode Work Function on Carbon-Nanotube Field-Effect Transistors

The effect of electrode work function (WF) on the device resistance of carbon-nanotube field-effect transistors (CNT-FETs) is less significant than that of device surface chemistry, specifically interactions with molecular oxygen adsorbate. Experimental results are based on over 130 individual devices with electrode WFs varying from 4.17 to 5.21 eV that were tested under standard-atmosphere, ultrahigh-vacuum, and pure-oxygen environments. Oxygen decreased device resistance by an average of 56% and altered majority charge carriers regardless of electrode metal. Variations in CNT-FET performance based on electrode material appeared more closely associated with crystallization and oxidation states than WF.

Novel attributes and design considerations of source and drain regions in carbon nanotube transistors

Source and drain regions are inseparable sections of carbon nanotube field effect transistor (CNTFET) whose parameters are effective for CNTFET performance. For the first time in this paper, design considerations of source and drain regions are presented by developing a two-dimensional (2-D) full quantum simulation. The simulations have been done by the self-consistent solution of 2-D Poisson–Schrödinger equations, within the nonequilibrium Green’s function (NEGF) formalism. The effects of varying the source and drain parameters are investigated in terms of on–off current ratio, transconductance characteristics, drain conductance, and subthreshold swing. Simulation results demonstrate that we could improve the CNTFET performance with proper selection of the source and drain parameters.

Monte Carlo study of coaxially gated CNTFETs: capacitive effects and dynamic performance

Carbon nanotubes (CNT) appear as a promising candidate to shrink field-effect transistors (FET) to the nanometer scale. Extensive experimental works have been performed recently to develop the appropriate technology and to explore DC characteristics of a carbon nanotube field effect transistor (CNTFET). In this work, we present results of a Monte Carlo simulation of a coaxially gated CNTFET, including electron–phonon scattering. Our purpose is to present the intrinsic transport properties of such material through the evaluation of the electron mean-free-path. To highlight the potential of the high performance level of CNTFET, we then perform a study of the DC characteristics and of the impact of capacitive effects. Finally, we compare the performance of CNTFET with that of a Si nanowire MOSFET. To cite this article: H. Cazin d'Honincthun et al., C. R. Physique 9 (2008).

Impact of axial strain on drain current of carbon-nanotube field-effect transistors with doped junctions

The effect of axial strain on the performance of carbon-nanotube field-effect transistors with doped junctions is studied. When the diameter of carbon nanotubes (CNTs) is less than 1.5nm, the decrease of the off-current by axial strain occurs together with the decrease of on-current. However, if the diameter of CNTs is larger than 1.5nm, axial strain is effective for decreasing off-current while enhancing the on-current at the same time. The decrease of off-current is due to the opening of the bandgap by axial strain, whereas the increase of on-current is attributable to current flowing through the first excited state.

High-frequency performance of multiple-channel carbon nanotube transistors

We have measured the high-frequency characteristics of carbon nanotube field effect transistors (CNTFETs) and obtained a cut-off frequency of 10.3 GHz and maximum oscillation frequency of 3.5 GHz. These values are among the highest ever published. We achieved them by developing a high-density multiple-channel CNTFET structure whose output impedance is much lower than conventional single channel CNTFETs, and by accurately measuring S-parameters, e.g., using the de-embedding procedure that removes existing errors in measured S-parameters of small-signal devices. We also described an equivalent circuit RF model consistent with the experimental results. Detailed analysis revealed that decreasing parasitic capacitances of electrodes and resistances of carbon nanotube extensions greatly improve the high-frequency performance of CNTFETs. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)