Abstract
Carbon Nanotube Field Effect Transistor (CNTFET) is one of the most promising candidates in the near future for digital design due to its better electrostatics and higher mobility characteristics. Parameters that determine the CNTFET performance are the number of tubes, pitch, diameter and oxide thickness. In this paper, a power gating design methodology to realise low power CNTFET digital circuits even under device parameter changes is presented. Investigation about the effect of different CNTFET parameters on dynamic and standby power is carried out. Simulation results reveal that the power gated circuits suppress a maximum of about 67% dynamic power and 59% standby power compared to conventional circuits.
Highlights
Power dissipation has become an important reliability issue in the design of submicron level digital devices
A low leakage charge recycling (LLCR) powergating technique designed for CMOS circuits has been tested with Carbon Nanotube Field Effect Transistor (CNTFET) digital circuits like an inverter, multiplexer, voltage controlled oscillator (VCO), and static random access memory (SRAM) cell for a low power dissipation
For evaluating the performance of the LLCR power gating structure, it is applied to inverter, 2 : 1 multiplexer, voltage controlled oscillator (VCO) and static random access memory (SRAM), as these are the basic circuits for a digital circuit design
Summary
Power dissipation has become an important reliability issue in the design of submicron level digital devices. Attempts on modelling and simulating CNTFETs [8, 9] are made for estimating their performance at the device level. The main idea of the paper is to reduce the power dissipation of CNTFET digital circuits by using a methodology called power gating. A low leakage charge recycling (LLCR) powergating technique designed for CMOS circuits has been tested with CNTFET digital circuits like an inverter, multiplexer, VCO, and SRAM cell for a low power dissipation. A power estimation is done for these digital circuits with and without the LLCR technique. The paper is organized as follows: Section 2 briefs about the structure and equivalent circuit of the CNTFET, and power gating techniques.
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