Carbon Nanotube-Based CMOS SRAM: 1 kbit 6T SRAM Arrays and 10T SRAM Cells

Abstract

We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate 1 kbit (1024) 6 transistor (6T) SRAM arrays fabricated with complementary metal-oxide-semiconductor (CMOS) CNFETs (totaling 6144 p- and n-type CNFETs), with all 1024 cells functioning correctly without any per-unit customization. Moreover, we show the first demonstration of CNFET CMOS 10T SRAM cells, capable of operating at highly scaled voltages down to 300 mV. We characterize the CNFET CMOS SRAM and demonstrate robust operation by writing and reading multiple patterns (to both the kbit arrays as well as the 10T SRAM cells), measuring SRAM variations in read, write, and hold margins and repeat cycling of cells. Moreover, due to the low-temperature back-end-of-line (BEOL)-compatible CNT-specific processing, CNFET SRAM enables new opportunities for digital systems, since: 1) CNFET SRAM can be fabricated directly on top of computing logic to realize three-dimensional integrated circuits; and 2) CNFET circuits can utilize metal routing both above and below the CNFET device layer (e.g., as in our demonstration which utilizes buried power rails, whereby the power rails are fabricated underneath the FETs while metal routing is fabricated above the FETs), providing opportunities for further SRAM density scaling.