Performance Of ASIC Research Articles

Initial performance assessment and calibration techniques of the production monolithic silicon pixel detector ASIC for the detection of electromagnetic showers of TeV energy in the FASER experiment at the LHC

The FASER experiment at the LHC aims to detect new, long-lived fundamental particles. A tungsten-silicon (W-Si) preshower detector is being developed to enhance the experiment's ability to distinguish between closely spaced photon pairs with energies on the order of TeV and separations as small as 200 µm. This detector will use a monolithic silicon pixel sensor fabricated with 130 nm SiGe BiCMOS technology. Initial tests were conducted on the production ASIC, after evaluating the performance of the preproduction ASIC. The first tests on the production ASIC indicate that the essential components of the monolithic silicon pixel detector are operating as expected. Two calibration methods were developed to reconstruct the charge of the FASER preshower detector, from the ASICs' ADC values.

Performance evaluation of the FastIC readout ASIC with emphasis on Cherenkov emission in TOF-PET

Objective. The efficient usage of prompt photons like Cherenkov emission is of great interest for the design of the next generation, cost-effective, and ultra-high-sensitivity time-of-flight positron emission tomography (TOF-PET) scanners. With custom, high power consuming, readout electronics and fast digitization the prospect of sub-300 ps FWHM with PET-sized BGO crystals have been shown. However, these results are not scalable to a full system consisting of thousands of detector elements. Approach. To pave the way toward a full TOF-PET scanner, we examine the performance of the FastIC ASIC with Cherenkov-emitting scintillators (BGO), together with one of the most recent SiPM detector developments based on metal trenching from FBK. The FastIC is a highly configurable ASIC with 8 input channels, a power consumption of 12 mW ch−1 and excellent linearity on the energy measurement. To put the timing performance of the FastIC into perspective, comparison measurements with high-power consuming readout electronics are performed. Main results. We achieve a best CTR FWHM of 330 ps for 2 × 2 × 3 mm3 and 490 ps for 2 × 2 × 20 mm3 BGO crystals with the FastIC. In addition, using 20 mm long LSO:Ce:Ca crystals, CTR values of 129 ps FWHM have been measured with the FastIC, only slightly worse to the state-of-the-art of 95 ps obtained with discrete HF electronics. Significance. For the first time, the timing capability of BGO with a scalable ASIC has been evaluated. The findings underscore the potential of the FastIC ASIC in the development of cost-effective TOF-PET scanners with excellent timing characteristics.

The optimization, design and performance of the FBCM23 ASIC for the upgraded CMS beam monitoring system

We present the development of the FBCM23 ASIC designed for the Phase-II upgrade of the Fast Beam Condition Monitoring (FBCM) system built at the CMS experiment which will replace the present luminometer based on the BCM1F ASIC [1]. The FBCM system should provide reliable luminosity measurement with 1 ns time resolution enabling the detection of beam-induced background. The FBCM23 ASIC comprises 6 channels of the fast front-end amplifier working in transimpedance configuration, booster amplifier, and leading edge discriminator. The complete processing chain provides an overall shaping function equivalent to the CR-RC3 filter. The paper will show the optimization of the design, overall architecture, and the detailed implementation in a CMOS 65 nm process as well as preliminary electrical performance.

Test and performance of the LiTE-DTU ASIC for the HL-LHC upgrade of the CMS ECAL barrel

A data conversion and compression ASIC, named LiTE-DTU, has been developed for the upgrade of the CMS electromagnetic calorimeter (ECAL) for the High-Luminosity phase of LHC. The ASIC integrates two 12-bit 160 MS/s ADCs, a data processing unit for gain selection and data compression, and a 1.28 Gb/s serializer.The ASIC has been extensively tested in laboratory and in beam tests showing excellent yield and performance. The radiation tolerance has been verified with dedicated test campaigns for both total ionizing dose and single event effects. Results from these tests, showing the design readiness for mass production, will be presented.

Recent developments in the IGNITE project on front-enddesign in CMOS 28-nm technology

The IGNITE project (INFN Ground-up INITiative-on micro-Electronics developments) is developing solutions on integrated micro-systems aimed at the next generation of high-luminosity experiment at the LHC. A test ASIC, designed in CMOS 28-nm technology and named Ignite-0, has been submitted for fabrication. It integrates circuital solutions suitable for pixels with timing having a pitch ranging from 45 to 55 µm. The present paper describes the criteria used in the design choices, and the expected ASIC performance as output from post-layout simulations. Perspectives on subsequent design work on 4D-tracking devices following the Ignite-0 development are also briefly described.

Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing

Sparse tensor algorithms are becoming widespread, particularly in the domains of deep learning, graph and data analytics, and scientific computing. Current high-performance broad-domain architectures, such as GPUs, often suffer memory system inefficiencies by moving too much data or moving it too far through the memory hierarchy. To increase performance and efficiency, proposed domain-specific accelerators tailor their architectures to the data needs of a narrow application domain, but as a result cannot be applied to a wide range of algorithms or applications that contain a mix of sparse and dense algorithms. This article proposes Symphony, a hybrid programmable/specialized architecture that focuses on the orchestration of data throughout the memory hierarchy to simultaneously reduce the movement of unnecessary data and data movement distances. Key elements of the Symphony architecture include (1) specialized reconfigurable units aimed not only at roofline floating-point computations but also at supporting data orchestration features, such as address generation, data filtering, and sparse metadata processing; and (2) distribution of computation resources (both programmable and specialized) throughout the on-chip memory hierarchy. We demonstrate that Symphony can match non-programmable ASIC performance on sparse tensor algebra and provide 31× improved runtime and 44× improved energy over a comparably provisioned GPU for these applications.

High-Density Pixel Imaging Sensor Readout Electronics for Space Applications: A Design Overview

With the specialization of VLSI ASICs for front-end signal processing electronics, the customization of the control back-end electronics (BEE) has become critical to fully deploy the ASIC performance. In the context of space operations, with typical constraints on power and reliability, the design and qualification of such integrated systems present significant challenges. In this paper, we review the design and performance of the BEE systems after two years of operations in low Earth orbit (LEO); these systems read out the custom ASICs inside the gas pixel detectors, which are located at the heart of the imaging X-ray polarimetry explorer (IXPE), a NASA-ASI small explorer mission designed to measure X-ray polarization in the 2–8 keV energy range.

On the Capacity Analysis Performance of ASIC Based Hybrid Full and Half Duplex User Relaying Cooperative NOMA System

On the Capacity Analysis Performance of ASIC Based Hybrid Full and Half Duplex User Relaying Cooperative NOMA System

Evaluation of the timing performance of the DIET ASIC

DIET is a 64-channel SiPM readout ASIC for TOF-PET and can measure energy and arrival time independently for each channel. With the increasing requirements for time measurement precision, the timing performance of the DIET chip has been fully evaluated in this paper. The noise sources in the time processing chain, especially in the TDC, were theoretically analysed, and a dedicated test system was built. The time jitter of the analogue front end and the TDC were measured and analysed. The test results show that the total jitters of the analogue front-end and the TDC are 24 ps and 22 ps RMS at 50 p.e. input signal, respectively. The percentages of the contribution by INL, thermal noise, and quantization noise of the TDC are 70%, 16.6%, and 13.4%, respectively. The DIET chip was also tested with SiPM and LYSO detectors. A CRT resolution of 244 ps FWHM was achieved using two single 3 × 3 × 16 mm3 crystals.

Performance characterization and radiation tolerance evaluation of the SSA2 ASIC, the strip sensor readout ASIC of the CMS Outer Tracker at the HL-LHC

This contribution presents the results of the performance characterization and radiation tolerance evaluation of the SSA2 ASIC, the short-strip readout ASIC for the CMS Outer-Tracker PS-module. The ASIC performance is characterised by different temperatures and operating conditions, at the die level as well as at the wafer level. The radiation evaluation comprises Total-Ionising-Dose (TID) tests and Single-Event-Effects (SEEs). Wafer-level testing provided a large dataset to evaluate the production yield. The presented test results are in agreement with the design simulations and are well within the application requirements for operation in the CMS outer-tracker at the HL-LHC.

Performance of ALTIROC2 readout ASIC with LGADs for ATLAS HGTD picosecond MIP timing detector

ALTIROC2 is a 225-channel ASIC designed in CMOS 130 nm to read out a 15 × 15 matrix of 1.3 mm × 1.3 mm Low Gain Avalanche Diodes (LGAD) for the ATLAS HGTD (High Granularity Timing Detector). The targeted combined time resolution of the sensor and its readout electronics range from 35 ps/hit (initial) to 65 ps/hit (end of operational lifetime). Each ASIC channel integrates a high-speed preamplifier followed by a high speed discriminator and two TDCs for Time-of-Arrival and Time-Over-Threshold measurements as well as a local memory. This front-end must exhibit a small jitter while keeping a challenging power consumption of less than 4.5 mW per channel. This conference proceeding summarizes the ASIC architecture, its measured performances compared to simulation, along with the requirements for the ATLAS HGTD experiments.

VLSI implementation of booth multiplier and carry select adder based fir filter design for ECG signal denoising

Over the last two decades, FIR filters have been the subject of intense research. The design of an adder, which is a major building component in circuit design, determines the overall performance of a system. The Finite Impulse Response (FIR) filter has been increasingly popular in signal processing applications in recent years. For signal processing field applications and VLSI systems, many adders are implemented. Signal denoising, as well as the production of an effective multiplier, had never been explained in any of the previous publications. This paper proposes 8 bit booth multipliers for partial products. The design employs the Carry select and Booth techniques. For partial product addition, the Carry Select Adder (CSA) is employed. The architecture of the FIR filter is proposed for operation with Electro Cardiogram (ECG) signal. It's known as CSA-BOOTH FIR, and it's used for denoising. Using the MATLAB application, the ECG signal with noise is sent into the filter. The denoising method is written in Verilog, with the output recorded in a text file. The binary values are read in MATLAB to denoise the signal. The performance of FPGAs and ASICs is evaluated.

Analysis and Optimization of the Performance of Hydrogenated Amorphous Silicon Solar Cell

As the name implies, hydrogenated amorphous silicon (a-Si: H) is composed of silicon atoms which are in a disordered configuration away from all Bravais lattices. The hydrogenated amorphous silicon was manufactured in 1969 where there was a renewed interest in non-hydrogenated amorphous silicon. The use of hydrogenated amorphous silicon as the active material in solar cells inefficient but cheap, is currently much studied. We have presented in this work, the results of the numerical simulation of a-Si: H solar cell by the wxAMPS (Analysis of Microelectronic and Photonic Structures) software and the results were compared with those found experimentally, we find a good agreement. For the efficiency there was a difference of 0.17%. We also study the influence of the thickness of a-Si: H intrinsic layer on the photovoltaic parameters of the solar cell. This allows considering the use of amorphous thinner layers for photovoltaic applications. The efficiency has a maximum value of 7.117 %, corresponding to a intrinsic layer thickness of 560 nm. The using a-Si:H alloys provide a good solution to enhance a-Si:H solar cell performance. The use of a-SiC:H as a p-type window layer in amorphous silicon solar cells is one of its primary photovoltaic applications. The wide band gap of p-a-SiC:H alloy used as window layer for minimizing the optical loss. To improve the efficiency of a-Si:H solar cell, we have study by simulation the performance of the (p) a-SiC:H/(i) a-Si:H/ (n) a-Si:H heterojunction solar cell. The effects of a-SiC:H window layer on the photovoltaic performance have been investigated, where the best initial conversion efficiency of 10.59%.

Design and first tests of the Gotthard-II readout ASIC for the European X-ray Free-Electron Laser

Gotthard-II is a charge-integrating microstrip detector developed for experiments and diagnostics at free-electron lasers using hard X-rays of 5 keV–20 keV. Thanks to its excellent single photon sensitivity, large dynamic range as well as high frame rate of 4.5 MHz in burst mode, its potential scientific applications include X-ray absorption/emission spectroscopy, hard X-ray high resolution single-shot spectrometry (HiREX), beam diagnostics, as well as veto signal generation for pixel detectors. The Gotthard-II ASIC has been designed and fabricated using UMC-110 nm technology. The final ASIC design and performance in terms of noise, linearity, dynamic range, coupling between channels and speed will be discussed in the paper. In addition, a first measurement of an X-ray absorption spectrum of a standard copper sample has been done. The performance of the Gotthard-II in an experiment using energy dispersive X-rays has been demonstrated.

100Gbps DMT ASIC for Hybrid LTE-5G Mobile Fronthaul Networks

Multiple access interfaces are required to provide the wireless coverage and capacity that operators need for consistent service across their geographic footprint. As a consequence, future radio access networks will be hybrid 4G/LTE-5G networks. This technology evolution is creating many challenges in the mobile fronthaul (MFH) networks to support the co-existence of common public radio interfaces (CPRI) and evolved common public radio interfaces (eCPRI) traffic with diverse connectivity requirements in term of capacity and reach. To address these challenges, this paper introduces a 100 Gb/s discrete multi-tone modulation (DMT) ASIC which has been designed and fabricated in 16 nm CMOS process, specifically targeting MFH applications. This DMT ASIC can flexibly support various important data rates in hybrid 4G/LTE-5G MFH networks, including CPRI-10, 25 GbE, 50 GbE, 75 GbE, and 100 GbE (eCPRI rates) over the full industrial temperature range (−40 °C to +85 °C). We demonstrate the high performance and reliability of this DMT ASIC in several real time transmission experiments, including: i) 200 Gb/s LAN-WDM2 transmission over 20 km in O-band using two 25-GHz class directly modulated lasers (DMLs); and ii) 200 Gb/s, 300 Gb/s and 400 Gb/s WDM transmissions over up to 40 km in C-band using 4 wavelengths, each with data rate of 50 Gb/s, 75 Gb/s, and 100 Gb/s, respectively. The success of these experiments clearly indicates the attractiveness of the presented DMT ASIC for future MFH applications. In addition, in several transmission scenarios, the advantages of DMT format over conventional PAM4 format for MFH applications are highlighted.

Design and performance of a silicon–tungsten calorimeter prototype module and the associated readout

We describe the details of a silicon-tungsten prototype electromagnetic calorimeter module and associated readout electronics. Detector performance for this prototype has been measured in test beam experiments at the CERN PS and SPS accelerator facilities in 2015/16. The results are compared to those in Monte Carlo Geant4 simulations. This is the first real-world demonstration of the performance of a custom ASIC designed for fast, lower-power, high-granularity applications.

Performance of a Front End prototype ASIC for picosecond precision time measurements with LGAD sensors

For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region, to mitigate the effects of the increased pile-up. The chosen detection technology is Low Gain Avalanche Detector (LGAD) silicon sensors that can provide an excellent timing resolution below 50 ps. The front-end read-out ASIC must exploit the large signal derivative and small noise provided by the sensor, while keeping low power consumption. This paper presents the results on the first prototype of a front-end ASIC, named ALTIROC0, which contains the analog stages (preamplifier and discriminator) of the read-out chip. The ASIC was characterised both alone and as part of a module with a 2×2 LGAD array of 1.1×1.1 mm2 pads bump-bonded to it. The various contributions of the electronics to the time resolution were investigated in test-bench measurements with a calibration setup. Both when the ASIC is alone or with a bump-bonded sensor, the jitter of the ASIC is better than 20 ps for an injected charge of 10 fC . The time walk effect, which arises from the different preamplifier response for various injected charges, can be corrected up to 10 ps using a Time Over Threshold measurement. The combined performance of the ASIC and the LGAD sensor, which was measured during a beam test campaign in October 2018 with pions of 120 GeV energy at the CERN SPS, is around 40 ps for all measured modules. All tested modules show good efficiency and time resolution uniformity.

Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising

Abstract In recent years, Finite Impulse Response (FIR) filter plays a major role in signal processing applications. Earlier many research papers are described the different types of FIR filter design. But, none of the paper explained about signal denoising application with an effective multiplier design. In this paper, Vedic Design - Carry Lookahead Adder FIR filter architecture is introduced to perform the FIR filter operation with Electro Cardiogram (ECG) signal de-noising application. By usingthe MATLAB program, the input ECG signal is read and Additive White Gaussian Noise (AWGN) is added to the input signal. The denoising process is implemented in Verilog and the obtained output is written in text files. For de-noising the signal, the binary text values are read in MATLAB. With the help of Verilog code, FPGA performance (LUT, flip flop, slices, and frequency) and ASIC performance (area, power, and delay) are evaluated. For ASIC implementation, 180 nm and 45 nm technology are used and for FPGA implementation Virtex-4, Virtex-5, and Virtex-6 devices are used to evaluate the performance. The Mean Square Error (MSE), Bit Error Rate (BER), and Signal to Noise Ratio (SNR) performance are calculated from the de-noised signal. In 180 nm technology, 42.39% of the area, 29.53% of delay, 43.89% of APP, 70.41% of ADP reduced in VD-CLA-FIR. In 45 nm technology, 13.2% of the area, 32.25% of the delay, 24.37% of APP, and 39.02% of ADP reduced in VD-CLA-FIR method compared to the conventional methods.

A Low-Power VLSI Implementation of RFIR Filter Design using Radix-2 Algorithm with LCSLA

ABSTRACT The multimedia applications and mobile communication systems require an efficient reconfigurable finite impulse response (RFIR) filter designs for achieving low area, power, cost, and high speed of system operation. In this paper, an efficient RFIR filter is designed based on the Radix-2 algorithm and Look-up-table Carry Select Adder (Radix 2 – LCSLA). Generally, the RFIR filter is controlled by multiplier and adder, which improves the performances of the filter. Hence, this research work is mostly concentrated on the multiplier and adder design. Here, the radix-2 algorithm is used instead of normal multiplier for multiplication operation in the RFIR filter design. Additionally, CSLA and LCSLA approaches used in the Radix-2 structure for adding partial products. The LCSLA has achieved better performance compared to the normal CSLA approaches. In this paper, both the Radix-2 algorithm and LCSLA approach improved the performances of the proposed RFIR filter design. The proposed RFIR filter design was implemented in the Xilinx and Cadence RTL compiler by using the Verilog code. The RFIR-Radix 2-LCSLA filter design was verified in the Modelsim by utilizing the Verilog code. The experimental result showed that the RFIR-Radix 2-LCSLA methodology has improved the performance of ASIC and FPGA in the RFIR filter design up to 5–15% compared to the existing filter architecture: DA-RFIR and LC-CBA-RFIR methods.

Design and performance of a TDC ASIC for the upgrade of the ATLAS Monitored Drift Tube detector

We present the prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC operation. This ASIC is based on a previously submitted demonstrator ASIC designed for timing performance evaluation, and includes all features necessary for the various operation modes, as well as the migration to the TSMC 130 nm CMOS technology. We present the TDC design with the emphasis on added features and performance optimization. Tests of the timing performance demonstrate that this ASIC meets the design specifications. The TDC has a bin size of about 780 ps, and a timing bin variations within 40 ps for all 24 channels with leading and trailing edge digitization, while the power consumption has been limited to 250 mW, corresponding to a consumption of about 5.2 mW per edge measurement.