Pentacene Organic Thin-film Transistors Research Articles

Impact of Scaling of Dielectric Thickness on Subthreshold Slope in Top-Contact Pentacene Organic Thin Film Transistors

In the present work, we have fabricated the bottom-gate top-contact configuration of the pentacene organic thin film transistors (OTFTs) using two different dielectric layers. The effect of scaling of poly(methyl methacrylate) (PMMA) and cross-linkable poly(4-vinyl phenol) (PVP) polymer dielectric thickness on the subthreshold slope (SS) in top-contact pentacene OTFTs was investigated. Subthreshold slope improved significantly with the scaling of the thickness of both dielectrics.

Low-Threshold pentacene OTFT by using NdTaON gate dielectric and ITO gate electrode

Ta-doped Nd oxynitrides (NdxTa(1-x)ON) are adopted as gate dielectrics in pentacene organic thin-film transistors on ITO glass for transparent applications. The device with Nd0.76Ta0.24ON can achieve the optimal performance with a high carrier mobility of 2.32 cm2/V·s and a small threshold voltage of −0.21 V. The capacitance–voltage results indicate that besides producing a high permittivity (high-k) for the gate dielectric, Ta incorporation in NdON can generate negative fixed charges in the oxide to assist the external gate voltage to produce a small threshold voltage. The threshold voltage is further reduced by the ITO gate electrode because ITO with higher work function can decrease the energy barrier for the charge-carrier injection at the source/channel interface. XPS and AFM reveal that the moisture resistance of pure Nd oxynitride can be enhanced by Ta doping to improve the smoothness of the dielectric surface, which results in weaker surface-roughness and grain-boundary scatterings, and consequently higher carrier mobility. The carrier mobility is further enhanced by the ITO gate electrode because similar to metal-gate/high-k stack, metallic ITO gate with higher electron concentration than Si gate can offer stronger screening effect on the carrier scattering induced by the severe atomic oscillation in the high-k NdTaON gate dielectric.

Naphthyl Methylacrylate Block Copolymer Insulators for Application in Pentacene Organic Thin-Film Transistors

Naphthyl Methylacrylate Block Copolymer Insulators for Application in Pentacene Organic Thin-Film Transistors

Low-Temperature-Processed High-Performance Pentacene OTFTs with Optimal Nd-Ti Oxynitride Mixture as Gate Dielectric

When processed at a low temperature of 200 °C, organic thin-film transistors (OTFTs) with pentacene channel adopting high-k Neodymium-Titanium oxynitride mixtures (NdTiON) with various Ti contents as gate dielectrics are fabricated. The Ti content in the NdTiON is varied by co-sputtering a Ti target at 0 W, 10 W, 20 W and 30 W, respectively, while fixing the sputtering power of an Nd target at 45 W. High-performance OTFT is obtained for the 20 W-sputtered Ti, including a small threshold voltage of −0.71 V and high carrier mobility of 1.70 cm2/V·s. The mobility improvement for the optimal Ti content can be attributed to smoother dielectric surface and resultant larger overlying pentacene grains as reflected by Atomic Force Microscopy measurements. Moreover, this sample with the optimal Ti content shows much higher mobility than its counterpart processed at a higher temperature of 400 °C (0.8 cm2/V·s) because it has a thinner gate-dielectric/gate-electrode interlayer for stronger screening on the remote phonon scattering by the gate electrode. In addition, a high dielectric constant of around 10 is obtained for the NdTiON gate dielectric that contributes to a threshold voltage smaller than 1 V for the pentacene OTFT, implying the high potential of the Nd-Ti oxynitride in future high-performance organic devices.

Preliminary Evaluation of Pentacene Field Effect Transistors with Polymer Gate Electret as Ionizing Radiation Dosimeters

Interest in the use of organic electronic devices in radiation sensing applications has grown in recent years. The numerous device configurations (e.g., diodes, thin film transistors) and potential for improved tissue equivalence compared to their silicon-based analogues make them attractive candidates for various radiation dosimetry measurements. In this work, a variation of the organic thin film transistor (OTFT) is studied, in which a polymer electret is added. An OTFT electret design can be used in either a wired or wireless configuration for in vivo dosimetry with the possibility of real-time detection. The linearity, reproducibility, and dependence on energy of these devices were measured through exposure to 100 kVp photons from an orthovoltage treatment unit (Xstrahl 300) and 6 MV photons from a Varian TrueBeam medical linear accelerator. Prior to irradiation, all transistors were programmed with a −80 V bias applied to the Gate electrode (Vg) for 3 s. In the wireless configuration, after each delivered dose, the transfer characteristic was scanned to readout the amount of erased charges by monitoring the drain current change. When the programmed charge was sufficiently depleted by radiation, transistors were reprogrammed for repeated use. The real-time readout in a wired configuration was performed by measuring the drain current with Vg = −15 V; Vd = −15 V. The 6 MV photon beam was turned on and off at different dose rates of 600, 400, 300, 200, and 60 cGy/min to quantify the sensitivity of the device to changes in dose rate. The wireless transistors showed a linear increase in current with increasing dose. The sensitivities for different energies were 60 ± 5 nA/Gy at 6 MV at a dose rate of 600 cGy/min and 80 ± 10 nA/Gy at 100 kVp at a dose rate of 200 cGy/min. The sensitivity of detectors tested in a wired configuration at Vd = −15 V; Vg = −15 V was 8.1 nA/s at a dose rate of 600 cGy/min. The principle of pentacene OTFTs with polymer electret as radiation detectors was demonstrated. Devices had excellent linearity, reproducibility, and were able to be reprogrammed for multiple uses as wireless detectors. The wired transistors demonstrated an effective response as real-time detectors.

Pentacene organic thin-film transistor based on Archimedean interdigitated spiral pattern

In this paper we describe the design, fabrication and technology for organic transistor OTFTs, in view of investigation of its I-V characteristic and capacitance. OTFTs are arising as emerging components for novel electric switches in digital circuits, inverter and primary power electronics components of PV systems. Moreover, they are emerging also in the explosive development of grid-connected markets, providing cost reductions and increasing efficiency. Specifically, here we analyze OTFTs whose pattern is based on two archimedean spirals. The novel aspect of this work is that the source/drain contacts are characterized by an Archimedean spiral shape, as opposed to the traditional rectangular shape. Main contributions of this work are: (i) the output characteristic curves of the OTFTs, (ii) the measurement of the capacitance of the entire device together with its analytical estimate and (iii) the validation through AFM that the geometry of the layers is coherent with that set during the fabrication of the OTFT.

Plasmon-phonon resonance at gate-electrode/gate-dielectric interface on carrier mobility of organic TFTs with high-k gate dielectrics

The resonance between the plasmons in gate electrode and the phonons in gate oxide of the omnipresent metal–oxidesemiconductor devices predicted in 2004 is experimentally demonstrated to degrade the mobility of the carriers in the semiconductor channel. By using bottom-gated pentacene organic thin-film transistors fabricated on n-type Si substrates with different resistivities, this work experimentally shows that even for thick HfLaO gate dielectric (~50 nm), the interaction between the gate plasmons and the dielectric phonons can significantly affect the carrier mobility. FTIR and Raman spectra reflect that the phonon frequency of the dielectric ranges from 13.2 to 24.9 THz, overlapping the gate-plasmon frequency (13.2 ~ 18.7 THz) of the 0.01 ~ 0.015 Ω·cm substrate. Therefore, the predicted mobility reduction can be explained by a simpler concept of “resonance”: when the oscillations of gate carrier and dielectric atom have about the same frequency, the remote phonon scattering of the gate dielectric on the channel carriers is greatly enhanced to reduce their mobility. In summary, this resonance-induced mobility reduction could pose a temperature-related reliability problem to electronic circuits when carrier freeze-out at low working temperature reduces the carrier density in the gate electrode to about 3 × 1018 cm−3 to result in a plasmon frequency close to the phonon frequency of the gate dielectric.

High-mobility pentacene organic thin-film transistors achieved by reducing remote phonon scattering and surface-roughness scattering

Pentacene organic thin-film transistors (OTFTs) with very high carrier mobility have been achieved on both rigid and flexible substrates by using high-k gate dielectric and metal gate. The high-k gate dielectric with suitable thickness can reduce the surface-roughness scattering, while the metal gate can suppress the remote phonon scattering. As a result, based on NbLaO gate dielectric, OTFTs with high carrier mobility of 10.6 cm2 V−1 s−1 (7.99 cm2 V−1 s−1) with the capacitance per unit area measured at frequency of 1 kHz and small threshold voltage of −0.92 V (−0.74 V) fabricated on Pd-coated Si substrate (Pd-coated vacuum tape) are realized, though they have rougher dielectric surface and smaller pentacene grains than their counterparts fabricated on n-Si substrate. Moreover, with the addition of 13-nm SiO2 interlayer between the NbLaO gate dielectric and metal gate electrode, the carrier mobility decreases by 71% and 65% for the OTFTs on Si and V.T. substrates, respectively, highlighting the importance of the RPS.

Performance Investigation of Organic Thin Film Transistor on Varying Thickness of Semiconductor Material: An Experimentally Verified Simulation Study

Physics-based two-dimensional numerical simulations are performed to analyze the device characteristics of tri-isopropylsilylethynyl (TIPS)-pentacene organic thin-film transistor (OTFT) fabricated using drop-casting technique. Further, using simulation technique enabling calibration this paper also presents the systematic study of the impact of active layer (TIPS-pentacene) thickness on device characteristics. The extracted parameters such as electric field intensity, current density, current On/Off ratio, and mobility exhibit variation with scaling down in active layer thickness from 500 to 100 nm. The study also revealed that Off current and On/Off current ratio (IOn/IOff) is highly dependent on the thickness of the semiconductor layer. Furthermore, the highest value of IOn/IOff is obtained at 100-nm thickness of TIPS-pentacene, which can be used for various fast-switching applications in digital circuits. Simulated results are not only reasonably matching with experimental results but also provide insight on charge transportation at the semiconductor-dielectric interface and in the bulk of TIPS-pentacene layer.

Reduced screening of remote phonon scattering in thin-film transistors caused by gate-electrode/gate-dielectric interlayer

Pentacene organic thin-film transistors have been fabricated with their NdTaO gate dielectrics annealed at 200 °C, 400 °C, and 800 °C to study the effects of remote phonon scattering caused by the thermal vibration of the gate dielectric on the carrier transport in the conduction channel. Although the sample annealed at 800 °C can achieve the best dielectric quality (reflected by its lowest oxide-charge density, smallest dielectric surface roughness, and largest pentacene grain size), it shows the lowest carrier mobility of 0.44 cm2/V·s as compared to the highest mobility of 1.69 cm2/V·s for the control sample without dielectric annealing. In addition, this mobility degradation increases with increasing annealing temperature in spite of improving dielectric quality. Transmission electron microscopy shows that higher annealing temperature results in the formation of a thicker Si-gate/gate-dielectric interlayer, which increases the separation between the Si-gate plasmons and the gate-dielectric dipoles to weaken the screening effect of the gate electrode on the remote phonon scattering of the high-k gate dielectric, resulting in a lower carrier mobility. Measurements at high temperatures also support the effects of the interlayer.

Organic Thin Film Transistors Fabricated by a Solution Process Using Direct Patterned Single-Layer Graphene Electrodes.

We propose the direct transfer method of single-layer graphene (SLG) from metal catalyst Cu-foil to a polymeric insulator and the direct patterning method of the SLG for electrodes of organic thin-film transistors (OTFTs) without contamination using soft-lithography. Through soft-lithography, SLG can be formed in various patterns relatively easily in comparison with the conventional photolithography method that has multiple complex process steps to make graphene patterns. Furthermore, the 6,13-bis(triisopropylsilylethynyl) pentacene OTFTs are fabricated in solution with SLG source and drain electrodes. As a result, the field-effect mobility of OTFTs based on SLG electrodes was enhanced about 4 times in comparison with that of OTFTs using typical metal electrodes due to the decrease in contact resistance.

Measurement of Channel Mobility in Top Contact Pentacene Organic Thin Film Transistors

Measurement of Channel Mobility in Top Contact Pentacene Organic Thin Film Transistors

Long-range crystal alignment with polymer additive for organic thin film transistors

In this work, we study for the first time the effect of a poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-HFP) polymer to control the crystal growth of solution-processed, small-molecule organic semiconductors and to improve the device performance of organic thin film transistors (OTFTs). A benchmark semiconductor 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) was employed to blend with the polymer additive. The TIPS pentacene blend film with 5% PVDF-HFP by weight ratio exhibited a significant morphology enhancement with crystals strictly aligned in long-range order. In particular, it showed an average grain width of 69.98 μm and a misorientation angle of 6.6°, which is a 3.5-fold increase and a 7-fold reduction as compared to the pristine TIPS pentacene film. The bottom-gate, top-contact TIPS pentacene OTFTs with PVDF-HFP polymer additive were fabricated. Electrical characterization showed a hole mobility of up to 0.1 cm2/Vs with 5% PVDF-HFP. The performance improvement of TIPS pentacene/PVDF-HFP based OTFTs can be attributed to the reduced amount of charge trap centers at the enlarged grain width, alleviated crystal misorientation and increased areal coverage. This facile approach to blend PVDF-HFP additive to align crystals and improve orientation in long-range order as demonstrated in this work can be useful for controlling the crystallization and charge transport of other small-molecule organic semiconductors for application in organic electronics on large-scale flexible substrate.

Gate Screening on Remote Phonon Scattering for Pentacene Organic TFTs: Holes Versus Electrons

Bottom-gated pentacene organic thin-film transistors (OTFTs) were fabricated on p-type and n-type Si wafers with different resistivities, with NdTaON as a high- ${k}$ gate dielectric. Although the pentacene grain size and dielectric surface roughness were nearly the same for all the samples, the carrier mobility improved with decreasing resistivity for both types of OTFTs (p-gate and n-gate), indicating that similar to the electron concentration, the hole concentration in the gate electrode can also affect the carrier mobility. This is attributed to the remote phonon scattering of the high- ${k}$ gate dielectric on the channel carriers, which can be screened by the holes in the gate electrode. The p-gate and n-gate samples with the lowest gate–electrode resistivity of $0.005~\Omega \cdot $ cm achieve the highest mobility of 1.15 and 1.37 cm $^{{2}}/\text{V}\cdot \text{s}$ , respectively. Moreover, for the same gate-doping concentration, the p-gate sample shows lower mobility than the n-gate sample. This is likely because under a negative gate voltage ( ${V}_{g}$ ), the p-gate is depleted to make the actual ${V}_{g}$ smaller than the applied ${V}_{g}$ , thus resulting in a lower extracted carrier mobility. In addition, such a depletion effect leads to a lower hole concentration near the gate–electrode/gate–dielectric interface, thus weakening the gate screening effect on the remote phonon scattering.

Polyacrylate polymer assisted crystallization: Improved charge transport and performance consistency for solution-processable small-molecule semiconductor based organic thin film transistors

Abstract In this study, we report on an effective approach to modulate crystallization, control charge transport and enhance performance consistency of small-molecule semiconductor based organic thin film transistors (OTFTs) with the addition of a polyacrylate polymer additive poly(2-ethylhexyl acrylate) (P2EHA). 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) was used as a benchmark semiconductor to blend with the P2EHA additive, leading to a vertical phase separation between these two components. The resultant TIPS pentacene film exhibited greatly reduced crystal misorientation, enlarged grain width and enhanced film coverage. Bottom-gate, bottom-contact OTFTs based on the TIPS pentacene/P2EHA blends were fabricated and showed an increased average hole mobility of 0.317 ± 0.047 cm2/V, as well as a performance consistency factor of 6.72, which is defined as the ratio of the average hole mobility to the standard deviation of mobility. Notably, it leads to a 10-fold and 7-fold enhancement of average mobility and performance consistency as compared to the pristine TIPS pentacene OTFTs. This great improvement of device performance can be attributed to the reduced crystal misorientation, less defects and trap centers at the grain boundaries as a result of the enlarged grain width, as well as increased film coverage, due to the addition of the P2EHA polyacrylate polymer additive.

Effects of source/drain-electrode material, thickness and fabrication method on the electrical performance of pentacene thin-film transistor

The effects of source/drain (S/D) electrode material (Ni, Pt and Pd) and deposition method (electron-beam evaporation and sputtering) on the performance of pentacene organic thin-film transistor (OTFT) are studied. Experimental results show that the OTFT with Pd S/D electrodes deposited by sputtering exhibits the best electrical performance. This should be due to the small charge-injection barrier at the pentacene/electrode interface and small thermal load generated during the metal deposition. Besides, through varying the Pd S/D electrode thickness, it is found that increasing the electrode thickness results in performance degradation due to degraded pentacene/electrode interface, which is caused by higher thermal stress developed during longer deposition time.

Effects of a Gate-Electrode/Gate-Dielectric Interlayer on Carrier Mobility for Pentacene Organic Thin-Film Transistors

Bottom-gated pentacene organic thin-film transistors with LaTiON gate dielectrics annealed at two different temperatures are fabricated on n+Si wafers. Although atomic-force microscopyresults indicate a smoother dielectric surface and larger pentacene grains for the sample annealed at 400 °C, this sample shows lower carrier mobility than the one annealed at 200 °C. Moreover, the crystallinity of the gate dielectrics is not a key factor in the degradation of the carrier mobility because both dielectrics remain amorphous according to TEM. However, the TEM results show that the sample annealed at 400 °C has a thicker dielectric/Si-gate interlayer. The resultant increase in gate electrode-to-dielectric distance weakens the gate screening of the remote phonon scattering, thereby degrading the mobility of the carriers in the pentacene channel. This effect can be further supported by two similar samples fabricated on n-Si wafers, in which the gate electrode with lower electron concentration has a reduced screening effect on the remote phonon scattering and results in a larger reduction in mobility for the 400 °C-annealed sample with thicker interlayer.

Onset voltage shift in the organic thin-film transistor with an atomic-layer-deposited charge-injection interlayer

Abstract High contact resistance at metal/organic interface is a general issue for organic thin-film transistors (OTFTs). We show that inserting an ultrathin vanadium oxide (VOx) interlayer by atomic layer deposition (ALD) at the metal/organic interface can greatly reduce the contact resistance and enhance the performance of pentacene OTFTs. When the ALD of VOx is performed at a relatively low temperature of 50 °C, the prepared transistor also exhibits a pronounced shift in onset voltage for several volts. The origin of this onset voltage shift is identified as the adsorption of dimethylamine, which is a byproduct of the ALD VOx process. We further show that the adsorption of dimethylamine can be well eliminated by elevating the ALD process temperature to 100 °C, which therefore offers a simple and straightforward approach to circumvent the issues with the onset voltage shift.

Effective performance improvement of organic thin film transistors by using tri-layer insulators

Organic thin film transistors (OTFTs) with silicon oxide (SiO2)/poly(4-vinylphenol) (PVP)/polymethylmethacrylate (PMMA) tri-layer structure (SPP) as dielectric layers have been fabricated. To verify the validity of such tri-layer structure, two different organic semiconductor materials such as p-type pentacene and n-type fluorinated copper phthalo–cyanine (F16CuPc) are both used for fabricating OTFTs. Comparing with the OTFTs even by using PMMA modification, the better interface quality existing between SPP dielectric and organic film leads a higher conductive efficiency for transport carriers in channel. And then the field effect carriers (hole in pentacene OTFTs and electron in F16CuPc OTFTs) mobilities are both increased obviously. Our results show the SPP dielectric structure can be widely used to improve performance of OTFTs.

Effects of Gate Electron Concentration on the Performance of Pentacene Organic Thin-Film Transistors

Bottom-gated pentacene organic thin-film transistors (OTFTs) with NdTaON as high-k gate dielectric have been fabricated on substrates with different resistivities: $0.005~\Omega ~ \cdot $ cm, $0.3~\sim ~0.9~\Omega ~ \cdot $ cm, and $1~\sim ~5~\Omega ~\cdot $ cm for n-Si wafers, and $35~\Omega $ /sq for ITO-coated glass. On the three n-Si substrates, the dielectric surface roughness and pentacene grain size are nearly the same, but the carrier mobility of the OTFTs show an obvious increase with decreasing resistivity, indicating that the gate electron concentration can affect the device performance. Despite the much larger dielectric surface roughness and smaller pentacene grain size, the OTFT on the ITO-coated glass shows the highest carrier mobility. These effects are attributed to remote phonon scattering on the channel carriers, which has been strongly screened by the electrons in the gate electrode. According to the measurement on the mobility degradation at high temperature, the remote phonon scattering is determined to be the dominant factor affecting the carrier mobility. As a result, the OTFT on ITO glass can achieve a high carrier mobility of 2.43 cm2/V $\cdot $ s and a small threshold voltage of −0.10 V.