Path Delay Research Articles

Adaptive generation of optical single-sideband signal with dually modulated EML

The optical single sideband (SSB) transmitter based on dual modulation of an electro-absorption modulation laser (D-EML) has attracted considerable attention for its capability of monolithic integration and high output power. A model-based modulation method has been developed recently for generating high-quality optical SSB signals with this D-EML scheme. However, this method requires accurate characterization of the EML’s chirps and pre-compensation for frequency responses of all-optical/electrical components, as well as the path difference between two driving signals. This imposes notable requirements on the transmitter characterization in practical applications. In this paper, we propose an adaptive method to approach the required responses of the pre-compensation filters for this optical SSB transmitter. This method avoids cumbersome device characterization and shows great resilience to the variation of system parameters. By using the proposed adaptive method, we generate a 56 Gb/s optical SSB orthogonal frequency-division multiplexed signal with the sideband suppression power ratio exceeding 21 dB. It is convenient with this method to switch the devices, i.e., directly modulated laser (DML) or electro-absorption modulator (EAM), to be pre-compensated for the optical SSB signal generation. Moreover, this method exhibits good tolerance to the path delay (±15 ps) between DML and EAM, as well as modulation depth. We also successfully transmit this signal over 80 km long standard single-mode fiber.

Overload cascading failure detection algorithm for multi-layer supply chain network considering delay probability factor

At present, the supply chain is multi-layered and complicated, and its failure detection is based solely on the characteristic threshold, which does not lack the ability to describe the complex supply chain. An overload cascading failure detection algorithm for multi-layer supply chain network considering delay probability is proposed. Based on the multi-layer supply chain network including raw material suppliers, manufacturers, distributors and retailers, the overload cascading failure model of the multi-layer supply chain network is constructed through networking, and the overload cascading failure process of the multi-layer supply chain network is described through three aspects: initial load, node capacity and overload node load distribution. By monitoring and analyzing the status update messages of each node in the supply chain network, and considering the delay probability factor, the node and path that may lead to cascading failure are identified by predicting the delay probability of the next message through the historical message delay probability, and the overload cascading failure detection of the multi-layer supply chain network is realized. The experimental results show that the algorithm can effectively detect the failure of each overloaded enterprise node in the multi-layer supply chain network, which is helpful to enhance the early warning and response ability of the cascade failure of the supply chain network. The algorithm can realize the failure detection of supply chain network under different attack conditions and initial failure ratio of nodes, and measure the anti-risk ability of supply chain network. Under deliberate attack and when the initial attack node is a supplier network layer node, it has a greater impact on the multi-layer supply chain network.

A lightweight dual-link accelerated authentication protocol based on NLFSR-XOR APUF

Physical Unclonable Function (PUF) circuits, as a lightweight hardware security primitive, can provide reliable authentication for resource-constrained Internet of Things (IoT) devices. However, in real-time environments and systems, authentication of embedded devices has strict requirements on resources and low latency. Therefore, this paper proposes a lightweight dual-link accelerated authentication protocol design based on NLFSR-XOR APUF, through the study of Non-Linear Feedback Shift Registers (NLFSR) and XOR APUF circuits. First, the scheme utilizes the symmetric path delay deviation characteristics of APUF and the complexity of NLFSR state transitions to form a nonlinear output function that changes with the challenge signal. Then, a lightweight and attack-resistant authentication protocol is established by combining the random probability of shuffling array bits with the XOR confusion mechanism. Finally, the advantages of GPU parallel computing and AES T-table reconfiguration scheme are used to achieve an accelerated and side-channel attack-resistant authentication protocol. Experimental results show that the PUF circuit can effectively resist various modeling attacks, including logistic regression (LR), artificial neural network (ANN), and support vector machine (SVM). The security of the protocol has been formally verified, and the prototype has been implemented on the Xilinx xc100T development board, effectively resisting deception attacks, physical attacks, and modeling attacks. The protocol's area overhead in terms of LUT and encryption time is reduced by 58.6 % and 67.8 %, respectively, compared to similar protocols.

Dynamic spatial price equilibrium, dynamic user equilibrium, and freight transportation in continuous time: A differential variational inequality perspective

In this paper we provide a statement of dynamic spatial price equilibrium (DSPE) in continuous time as a basis for modeling freight flows in a network economy. The model presented describes a spatial price equilibrium due to its reliance on the notion that freight movements occur in response to differences between the local and distant prices of goods for which there is excess demand; moreover, local and distant delivered prices are equated at equilibrium. We propose and analyze a differential variational inequality (DVI) associated with dynamic spatial price equilibrium to study the Nash-like aggregate game at the heart of DSPE using the calculus of variations and optimal control theory. Our formulation explicitly considers inventory and the time lag between shipping and demand fulfillment. We stress that such a time lag cannot be readily accommodated in a discrete-time formulation. We provide an in-depth analysis of the DVI's necessary conditions that reveals the dynamic user equilibrium nature of freight flows obtained from the DVI, alongside the role played by freight transport in maintaining equilibrium commodity prices and the delivered-price-equals-local-price property of spatial price equilibrium. By intent, our contribution is wholly theoretical in nature, focusing on a mathematical statement of the defining equations and inequalities for dynamic spatial price equilibrium (DSPE), while also showing there is an associated differential variational inequality (DVI), any solution of which is a DSPE. The model of spatial price equilibrium we present integrates the theory of spatial price equilibrium in a dynamic setting with the path delay operator notion used in the theory of dynamic user equilibrium. It should be noted that the path delay operator used herein is based on LWR theory and fully vetted in the published dynamic user equilibrium literature. This integration is new and constitutes a significant addition to the spatial price equilibrium and freight network equilibrium modeling literatures. Among other things, it points the way for researchers interested in dynamic traffic assignment to become involved in dynamic freight modeling using the technical knowledge they already possess. In particular, it suggests that algorithms developed for dynamic user equilibrium may be adapted to the study of urban freight modelled as a dynamic spatial price equilibrium. As such, our work provides direction for future DSPE algorithmic research and application. However, no computational experiments are reported herein; instead, the computing of dynamic spatial price equilibria is the subject of a separate manuscript.

Clock synchronization characterization of the Washington DC metropolitan quantum network (DC-QNet)

Quantum networking protocols relying on interference and precise time-of-flight measurements require high-precision clock synchronization. This study describes the design, implementation, and characterization of two optical time transfer methods in a metropolitan-scale quantum networking research testbed. With active electronic stabilization, sub-picosecond time deviation (TDEV) was achieved at integration times between 1 and 105 s over 53 km of deployed fiber. Over the same integration periods, 10-ps level TDEV was observed using the White Rabbit–Precision Time Protocol over 128 km. Measurement methods are described to understand the sources of environmental fluctuations on clock synchronization toward the development of in situ compensation methods. Path delay gradients, chromatic dispersion, polarization drift, and optical power variations all contributed to clock synchronization errors. The results from this study will inform future work in the development of compensation methods essential for enabling experimental research in developing practical quantum networking protocols.

Anti-machine-learning-attack strong PUF design based on multi-path delay selection strategy

Physical unclonable functions (PUF) have significant potential for application in information security. However, strong PUFs are vulnerable to machine learning (ML) modeling attacks, which severely limit their application in device authentication. Despite a variety of resistance techniques, strong PUFs suffer from hardware cost and stability deficiencies. This study proposes an anti-machine-learning-attack strong PUF based on a multi-path delay selection strategy through research on the entropy source of a strong PUF and the delay signal selection mechanism. First, we constructed a deviation source circuit based on multiplexers to increase the diversity of the delay signal transmission paths. Second, we constructed a delay selection circuit based on the logic gates. This circuit dynamically selects the delay signals with the same transmission path in the deviation source using AND and OR gates. Subsequently, the deviation source and delay selection circuits were utilized to construct the delay module, and the interconnection module was inserted between the delay modules to achieve alternating appearances of different types of logic gates along the delay path. Finally, RS flip-flops were employed to make decisions on the bias signals with the same delay path, and the final response was output through an XOR operation. The proposed PUF was implemented on a Xilinx Artix-7 FPGA, and the prediction accuracy of the four typical ML models was below 59 % (with 500,000 challenge-response pairs as the training set). Moreover, the proposed PUF structure is scalable and exhibits better performance in terms of hardware cost and stability than existing classic structures.

Towards fine-grained load balancing with dynamical flowlet timeout in datacenter networks

In modern datacenter networks (DCNs), load balancing mechanisms are widely deployed to enhance link utilization and alleviate congestion. Recently, a large number of load balancing algorithms have been proposed to spread traffic among the multiple parallel paths. The existing solutions make rerouting decisions for all flows once they experience congestion on a path. They are unable to distinguish between the flows that really need to be rerouted and the flows that potentially have negative effects due to rerouting, resulting in frequently ineffective rerouting. Fine-grained rerouting will also cause severe packet reordering, especially in asymmetric topology scenarios. To address the above issues, we present a fine-grained traffic-differentiated load balancing (TDLB) mechanism, which aims to distinguish flows that are necessarily to be rerouted and reroute traffic in fine-grained without packet reodering. Specifically, TDLB distinguishes the traffic that must be rerouted through the host pair information in the packet header, and selects an optimal path for rerouting. To prevent severe packet reodering caused by excessive path delay differences, TDLB dynamically adjusts the flowlet timeout to segment the traffic and select the optimal path for rerouting. The NS-2 simulation results show that TDLB effectively reduces tail latency and average flow completion time (FCT) for short flows by up to 49% and 46%, respectively, compared to the state-of-the-art load balancing schemes.

HEAD: High-Speed Approximate HEterogeneous ADder for Error-Resilient Applications

Media processing applications can tolerate error up to a certain limit due to the perceptual limitations of the human eye. Since adders are ubiquitous in power-hungry media processing applications, they can be approximated without much compromise in quality. An adder with better error characteristics without significant compromise in area and power is required to meet the future demands of ever-increasing computational needs. In order to achieve the same, a novel segmentation technique has been proposed. By varying the number of bits in each segment, three different designs are proposed, each with its advantage. Each proposed adder is segmented into three portions, namely Most Significant Portion (MSP), Intermediate Significant Portion (ISP) and Least Significant Portion (LSP). The sub-adder’s sum in each portion is computed concurrently to reduce the critical path delay. The proposed heterogeneous adder (HEAD) designs achieve better accuracy than the state-of-the-art designs. Synthesis results show that HEAD consumes less area up to 41.8% and consumes less power ranging from 0.8% to 51%, than existing adders. Exhaustive simulations are carried out on benchmarking image sharpening application to prove that the proposed adders obtain a better quality-effort tradeoff than the existing designs.

Design and Implementation of Optimized PCI Express Physical Layer for High-Speed and Low-Latency Data Transfer

The PCIe (Peripheral Component Interconnect Express) Protocol is crucial for establishing high-speed data communication between computer peripherals, such as graphics cards and network cards etc. This communication protocol is transmitting data in packet format, with each packet containing both data and destination address and other essential information for accurate data delivery. This paper focused on Physical Layer to achieve High-Speed Data Transmission by reducing delay parameter. To minimize disturbances and enhance reliability, the physical layer uses scrambling technique and an 8b – 10b encoding technique is used for synchronization and error detection. Additionally, SIPO and PISO converts data format to improve efficiency and accuracy. The design is implemented using the Cadence compiler targeting 45nm process technology. This design is delay efficient resulting in path delay of 5.0ns and the operating frequency of 200MHz, power consumption of 1.2mw and an area of 1999µm².

Off-axis digital lensless holographic microscopy based on spatially multiplexed interferometry.

Digital holographic microscopy (DHM) is a label-free microscopy technique that provides time-resolved quantitative phase imaging (QPI) by measuring the optical path delay of light induced by transparent biological samples. DHM has been utilized for various biomedical applications, such as cancer research and sperm cell assessment, as well as for in vitro drug or toxicity testing. Its lensless version, digital lensless holographic microscopy (DLHM), is an emerging technology that offers size-reduced, lightweight, and cost-effective imaging systems. These features make DLHM applicable, for example, in limited resource laboratories, remote areas, and point-of-care applications. In addition to the abovementioned advantages, in-line arrangements for DLHM also include the limitation of the twin-image presence, which can restrict accurate QPI. We therefore propose a compact lensless common-path interferometric off-axis approach that is capable of quantitative imaging of fast-moving biological specimens, such as living cells in flow. We suggest lensless spatially multiplexed interferometric microscopy (LESSMIM) as a lens-free variant of the previously reported spatially multiplexed interferometric microscopy (SMIM) concept. LESSMIM comprises a common-path interferometric architecture that is based on a single diffraction grating to achieve digital off-axis holography. From a series of single-shot off-axis holograms, twin-image free and time-resolved QPI is achieved by commonly used methods for Fourier filtering-based reconstruction, aberration compensation, and numerical propagation. Initially, the LESSMIM concept is experimentally demonstrated by results from a resolution test chart and investigations on temporal stability. Then, the accuracy of QPI and capabilities for imaging of living adherent cell cultures is characterized. Finally, utilizing a microfluidic channel, the cytometry of suspended cells in flow is evaluated. LESSMIM overcomes several limitations of in-line DLHM and provides fast time-resolved QPI in a compact optical arrangement. In summary, LESSMIM represents a promising technique with potential biomedical applications for fast imaging such as in imaging flow cytometry or sperm cell analysis.

IoT-driven optimization of a NxN enhanced pipeline multiplier

As the Internet of Things (IoT) continues to evolve, the demand for efficient hardware solutions is crucial. The paper explores the significance of hardware multiplication in IoT devices and discusses the challenges and opportunities in implementing dedicated hardware accelerators for multiplication operations. It specifically focuses on a highly efficient NxN-bit folded pipeline multiplier designed using advanced 22 nm CMOS technology and a modified hierarchical design approach. This multiplier achieves remarkable performance enhancements by reducing critical path delay through pipelining, resulting in a three-fold increase in operational speed compared to conventional multipliers. Additionally, it consumes only 0.2 mW of power and reduces chip area consumption by over 28 %. The paper emphasizes the importance of minimizing computational latency and power consumption to enable IoT devices to execute complex algorithms with improved speed and resource utilization. It also addresses trade-offs, such as area overhead and design flexibility, associated with hardware multiplication. The insights provided contribute to ongoing efforts to optimize hardware components for IoT applications, fostering the development of more capable and responsive IoT ecosystems. The study presents a rapid and energy-efficient alternative for multiplication in digital hardware, addressing the need for high-performance and energy-efficient devices in the context of the IoT.

Virtual feedback control of interior road noise based on headrest loudspeakers

This paper analyzes the factors that affect the noise reduction performance of feedback control based on remote microphone technique (RMT) and how these factors can be exploited to improve the control performance. First, simulations were conducted to compare the noise reduction performance of employing feedback control directly at the virtual microphone (located at the ear position) and on the physical microphone (located on the headrest), as well as the RMT-based feedback control system. Then the impact of the delay of the virtual secondary path and the coherence between physical and virtual signals on the noise reduction performance of the RMT-based feedback control system was analyzed. It is found that the noise reduction performance can be improved by reducing the delay of the virtual secondary path or increasing the number of physical microphones. Finally, experiments of a dual-channel control system conducted inside an electric car cabin demonstrate that the feedback control strategy based on RMT achieves a binaural noise reduction of 3.4 dBA when employing 4 physical microphones to estimate sound pressure at the ear positions. This approach achieves similar performance but is more cost-effective than a feedforward system using multiple reference sensors.

TSTL-GNN: Graph-Based Two-Stage Transfer Learning for Timing Engineering Change Order Analysis Acceleration

Timing Engineering Change Order (ECO) is time-consuming in IC design, requiring multiple rounds of timing analysis. Compared to traditional methods for accelerating timing analysis, which focus on a specific design, timing ECO requires higher accuracy and generalization because the design changes considerably after ECO. Additionally, there are challenges with slow acquisition of data for large designs and insufficient data for small designs. To solve these problems, we propose TSTL-GNN, a novel approach using two-stage transfer learning based on graph structures. Significantly, considering that delay calculation relies on transition time, we divide our model into two stages: the first stage predicts transition time, and the second stage predicts delay. Moreover, we employ transfer learning to transfer the model’s parameters and features from the first stage to the second due to the similar calculation formula for delay and transition time. Experiments show that our method has good accuracy on open-source and industrial applications with an average R2score/MAE of 0.9952/13.36, and performs well with data-deficient designs. Compared to previous work, our model reduce prediction errors by 37.1 ps on the modified paths, which are changed by 24.27% on average after ECO. The stable R2 score also confirms the generalization of our model. In terms of time cost, our model achieved results for path delays consuming up to 80 times less time compared to open-source tool.

Adaptive prairie dog optimization based variable length conditional counter for designing multiplier

Binary counters (BC) are electronic devices that are used for counting the particular events that have been happened, followed by storing and displaying the count numbers. BC includes clock signal with sequential logic circuit for the effectuation of counting operation. It is used in many applications like FM decoders to memory chips. In this work we designed a serial multiplier using the proposed Adaptive Prairie Dog optimization (APDO) based variable length conditional counter (VLCC) for the mitigation delay. The suggested work is motivated by the need for an efficient multiplier design to mitigate delay. Mitigating delay in multiplier design is essential for various reasons, particularly in the fields of digital signal processing, computer arithmetic, and high-performance computing. The proposed technique is used to design the multiplier with reduced path delay and enhances the slack interval with various frequencies. The maximized frequency operation is evaluated with the slack interval of the circuit. Simulations are made using Mentor Graphics EDA simulator tool and analyzed the slack time and compared with state-of-art works. The implementation of 8-bit binary multiplier is effectuated in CMOS technology. Our proposed design surpasses all the other design in terms of mitigated computational delay and enhanced slack time. At higher frequency, the proposed method offers improved slack time of 14 % and 68 % of multiplier circuit to reduce delay. Due to the simulation investigations, 18 % slack time improved and reduce 87 % to the critical path delay when compare 45 nm with the 350-nm CMOS technology.

DRL-Tomo: a deep reinforcement learning-based approach to augmented data generation for network tomography

Abstract Accurate and current comprehension of network status is crucial for efficient network management. Nevertheless, direct network measurement strategies entail substantial traffic overhead and demand intricate coordination among network entities, making them impractical. Network tomography, an indirect measurement approach, utilizes insights garnered from measured parts to deduce characteristics of the entire network. Past studies frequently depend on acquiring challenging-to-access information, such as the complete network topology or support from specialized protocols. Unfortunately, these constraints pose challenges in non-cooperative scenarios where obtaining such information is difficult. Recent endeavors pursue emancipating tomography from dependence on copious information, striving to predict unmeasured path performance using limited data. Nevertheless, the disparity between the measured data and actual performance has hindered the accuracy. In response, we introduce an innovative tomography framework named DRL-Tomo, designed to alleviate potential biases. DRL-Tomo initiates by generating augmented data through deep reinforcement learning, gradually approximating the genuine performance of unmeasured paths. Subsequently, a neural network model is trained using this augmented data, enabling precise inferences. Our experiments, encompassing both real-world and synthetic datasets, vividly demonstrate DRL-Tomo’s remarkable enhancement. Specifically, it achieves a substantial 10%–67% improvement in path delay prediction and an impressive 30%–98% enhancement in path loss rate prediction.

An optimized design of delay-and energy-efficient Booth multiplier

Multipliers are essential computation units in virtually all computing systems, including processors and numerous AI accelerator architectures. This paper presents an optimized architecture for a Booth multiplier, targeting high performance while minimizing energy consumption and area utilization. The design optimization focuses on all three multiplier stages: partial product generation, reduction, and summation. To enhance delay and energy efficiency in the partial product generation stage, we first employed a simplified configuration comprising inverters and a sign selection unit instead of complex binary-to-two's complement circuitry. Next, to achieve further delay and area efficiency at this stage, logic optimization is applied at the partial product's generation circuitry by designing Booth encoders to remove redundant logic in multiplexers circuitry. Moreover, we introduced specialized sign compressors tailored for carry-save compression in the compression stage. Compared to conventional counterparts, these compressors offered lower power consumption and reduced critical path delay with only two XOR logic gates. Finally, in the summation stage, we proposed an optimized design segment for Carry Look-Ahead Adder for the final summation stage, designed to deliver swift throughput with minimal fan-in logic gates, even in the context of high bit-width configurations. This segment is cascaded to make a 13-bit final adder for the summation stage in the proposed design. The proposed architecture undergoes ASIC-targeted synthesis in Cadence Genus employing FreePDK CMOS 45 nm process technology. Synthesized results, along with theoretical design complexity comparison, demonstrate that the proposed design surpasses state-of-the-art 8 × 8 multiplier designs by critical metrics, including delay, power consumption, area utilization, power delay product, and area delay product.

Multi‐band millimetre wave indoor directional channel measurements and analysis for future wireless communication systems

AbstractSingle‐input single‐output (SISO) three‐dimensional (3D) wideband indoor directional measurements collected in a factory environment and an office environment at 38 and 70 GHz are presented. 3D single‐input multiple‐output (SIMO) dual polarised measurements with 1 × 2 antenna configurations were also carried out in a meeting room, a conference room, and an office room at the 60 GHz band. The measurements cover both azimuth and elevation by rotating the directional antenna (RDA) at the receiver side. Different statistical channel parameters such as power delay profile, power angle profile, root‐mean‐square delay spread, angular spread, and path loss were estimated for different possible antenna orientations between the transmitter and the receiver, which include line‐of‐sight, obstructed line‐of‐sight, and non‐line‐of‐sight. The polarisation effects on path loss models and the delay and angular spread models based on the surface area of the environment are studied. The results will be valuable for the design of indoor millimetre wave cellular networks.

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

Toward reliability-satisfied and hop-constrained backup paths for industrial internet demands

Industrial data transfer must rapidly recover from possible link failures to ensure reliability. The backup path mechanism is one of the transfer protections against multiple link failures. In this paper, we study a reliability-satisfied and hop-constrained backup path model that strives to reduce network capacity consumption under constraints on the reliability and maximum hop number of the backup path. The constraint on the maximum hop number is used to ensure the reliability and delay of a backup path. We propose an approximation algorithm to solve the dynamic backup path arrangement problem that is NP-hard.

An aging simulation method based on the change of input vector inside the critical path

Abstract With the large-scale expansion and process shrinking of modern integrated circuits, aging has become one of the main factors threatening circuit reliability. To evaluate the impact of aging on circuit life, it is important to investigate aging simulation methods. Aiming at the problem of slow speed and insufficient accuracy of large-scale digital circuit aging simulation methods, a circuit aging simulation method based on the change of input vector inside the critical path (CICP) is proposed in this paper. First, the critical path (CP) with the tightest timing is extracted by static timing analysis (STA), and SPICE simulation is carried out to accurately predict the aging of the CP of the circuit. Second, the aging simulation is carried out considering the change of the internal input vector of the CP. The simulation results show that after changing the internal input signal, the aging path delay increases up to 3.5%.