Path Delay Research Articles

Packets distribution over asymmetric paths using concurrent multipath transfer

AbstractConcurrent multipath transfer (CMT) is a transport layer protocol used for transferring data over multiple paths concurrently. In the case of asymmetric paths, the dissimilarity of delay, bandwidth, and loss rate among paths leads to challenges such as out‐of‐order packets, receiver buffer blocking, and throughput reduction. A framework that uses the end‐to‐end delay of paths to distribute the packets over asymmetric paths in ordering policy is proposed. The proposed framework detects network congestion in the assigned path and reduces the congestion window. Furthermore, the proposed framework predicts receiver buffer blocking and deactivates the highest delay path that causes this problem. The simulation results show that the proposed framework achieves highest throughput, lower entropy and lower average application end‐to‐end delay than the previous algorithms.

Modified SiP single-polarization CADD receiver.

In cost-sensitive application scenarios, increasing the data rate per channel under a limited receiver bandwidth is critical, and thus, the transceivers with low costs and high electrical spectral efficiencies (ESEs) are highly desirable. In this Letter, we demonstrate a modified silicon photonic (SiP) carrier-assisted differential detection (CADD) receiver with a record ESE for single polarization. The ESE of the conventional CADD is mainly limited by the transfer function that originated from the optical delay and hybrid. We modify the transfer function of the CADD by placing an additional delay in parallel to the original delay path. Consequently, the modified transfer function exhibits a sharper slope around the zero frequency, leading to a higher ESE. Here we employ complementary metal-oxide-semiconductor-compatible SiP integration to further reduce the cost and footprint of the modified CADD receiver. In the experiment, 280-Gb/s raw rate (net 226-Gb/s) 16-QAM OFDM signal after 80-km SMF transmission was detected using a 36.5-GHz SiP modified CADD receiver, with a bit error ratio below the 24% SD-FEC threshold. To our best knowledge, we achieve a record net 6.2-b/s/Hz ESE for an integrated single-polarization DD receiver with a 16-QAM format.

Centralized multicasting AODV routing protocol optimized for intermittent cognitive radio ad hoc networks

The advancement of wireless technology is affected by Spectrum scarcity and the overcrowding of free spectrum. Cognitive Radio Ad Hoc Networks (CRAHNs) have emerged as a possible solution to both the scarcity and overcrowding challenges of the spectrum. The CRAHNs ensure that the Secondary Users (SUs) do co-exist with Primary Users (PUs) in a non-interfering manner. The SUs access the licensed spectrum opportunistically when they are idle. CRAHNs have many use cases which include intermittent networks here referred to as intermittent CRAHNs (ICRAHNs). For example, the Military (MCRAHNs). MCRAHN is complex and characterized by a dynamic topology which is subject to frequent partitioning and route breakages due to attacks and destruction in combat. This study optimizes the routing protocols for intermittent networks such as the MCRAHNs. ICRAHN routing is a challenge due to the network’s intermittent attribute, which is subject to destruction in the case of MCRAHN which is characterized by frequent link breakages. To better understand the routing in this network scenario, this paper presents two analytic models for the AODV and MAODV protocols based on queuing theory. The analytic models simulate unicast and multicast AODV in terms of factors such as queuing delay, throughput, and network scalability. Numerical analysis shows that MAODV outperforms AODV. Furthermore, the suggested routing protocols' performance was tested using network simulations utilizing the following metrics: throughput, Routing Path delay, Node Relay delay, and Spectrum Mobility delay. The simulation findings suggest that the MAODV protocol outperforms the AODV protocol.

A Real-time P-SFA hardware implementation of Deep Neural Networks using FPGA

Machine Learning (ML) algorithms, specifically Artificial Neural Networks (ANNs), have proved their effectiveness in solving complex problems in many different applications and multiple fields. This paper focuses on optimizing the activation function (AF) block of the NN hardware architecture. The AF block used is based on a probability-based sigmoid function approximation block (P-SFA) combined with a novel real-time probability module (PRT) that calculates the probability of the input data. The proposed NN design aims to use the least amount of hardware resources and area while maintaining a high recognition accuracy. The proposed AF module in this work consists of two P-SFA blocks and the PRT component. The architecture proposed for implementing NNs is evaluated on Field Programmable Gate Arrays (FPGAs). The proposed design has achieved a recognition accuracy of 97.84 % on a 6-layer Deep Neural Network (DNN) for the MNIST dataset and a recognition accuracy of 88.58% on a 6-layer DNN for the FMNIST dataset. The proposed AF module has a total area of 1136 LUTs and 327 FFs, a logical critical path delay of 8.853 ns. The power consumption of the P-SFA block is 6 mW and the PRT block is 5 mW.

Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins

Placement is a critical step in the physical design for digital application specific integrated circuits (ASICs), as it can directly affect the design qualities such as wirelength and timing. For many domain specific designs, the demands for high performance parallel computing result in repetitive hardware instances, such as the processing elements in the neural network accelerators. As these instances can dominate the area of the designs, the runtime of the complete design’s placement can be traded for optimizing and reusing one instance’s placement to achieve higher quality. Therefore, this work proposes a mixed integer programming (MIP)-based placement refinement algorithm for the repetitive instances. By efficiently modeling the rectilinear steiner tree wirelength, the placement can be precisely refined for better quality. Besides, the MIP formulations for timing-driven placement are proposed. A theoretical proof is then provided to show the correctness of the proposed wirelength model. For the instances in various popular fields, the experiments show that given the placement from the commercial placers, the proposed algorithm can perform further placement refinement to reduce 3.76%/3.64% detailed routing wirelength and 1.68%/2.42% critical path delay under wirelength/timing-driven mode, respectively, and also outperforms the state-of-the-art previous work.

Optimizing multiplier design for enhanced processor performance

In processor design, the multiplier serves as a critical component whose operational speed and efficiency directly impact the performance of the processor. To meet the demands of rapidly advancing technology, enhancing processor performance is of paramount importance. The crux of multiplier design lies in reducing the count of partial products and compressing them. This paper presents the design of a multiplier that utilizes the Booth algorithm and the Wallace tree structure for optimization, along with the incorporation of registers for secondary pipeline processing to further elevate efficiency. The Booth algorithm selects the base-4 Booth algorithm, effectively reducing the count of partial products and mitigating the optimization efficiency reduction caused by circuit complexity. The Wallace tree structure employs a combination of 3-2 and 4-2 compressors, resulting in decreased resource consumption and reduced critical path delays. This paper outlines a step-by-step introduction to these three optimization methods and conducts simulations and tests on the current multiplier after each optimization step. Through simulation analysis, this paper confirms the success of the design and provides insights and outcomes to the current field of multiplier optimization, aiming to ultimately drive advancements in processor performance.

A design of multiplier based on Radix_4 Booth algorithm and 4-2 Wallace compression tree

In a multitude of computational and signal processing scenarios, the multiplier functions as a fundamental arithmetic component. Given the complex hardware arrangement of multipliers and their usual positioning within the crucial pathway of digital systems, their significance is substantial. Therefore, approximations of multipliers can greatly optimize system performance. This essay examines the fundamental ideas behind the Wallace tree, the Carry ahead adder, and the Radix-4 Booth algorithm. Additionally, instead of the more common 3-2 compressors, a Wallace tree structure with 4-2 compressors is used to compact these products for the manufacture of partial products. This reduction in compression stages to three significantly curtails delays along critical paths, thereby substantially improving overall performance. The compressed outcomes from the Wallace tree undergo processing via a 64 bit carry ahead adder, effectively addressing delays stemming from mutual carry propagation among sequentially connected regular full adders. Leveraging these principles and processes, a 32-bit signed multiplier is designed. Building upon this foundation, an approximate Booth multiplier is developed, enhancing both computational speed and reducing critical path delays. The functionality of the multiplier was validated using Vivado simulation, demonstrating its correctness. Additionally, the RTL-level circuitry of different segments of the multiplier was showcased.

Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations

Binary Three-operand adder serves as a foundation block used within security and Pseudo Random-Bit Generator (PRBG) systems. Binary Three-operand adder was designed using Carry Save Adder but this consumes more delay. Therefore, a Parallel Prefix Adder (PPA) method can be utilized for faster operation. The canonical types of PPA result in a lesser path delay of approximately O (log2 n). These adders can be designed for 8, 16, 24 or n bits. But this work is focused on developing a 24-bit three-operand adder that takes three 24-bit binary numbers as input and generates a 24-bit sum output and a carry using five different PPA methods The proposed summing circuits are operationalized with Hardware-Description-Language (HDL) using Verilog, and then subjected to synthesis using Field -Programmable Gate- Array (FPGA) Vertex 5. On comparing the proposed adders, it shows that the delay and the size occupied are significantly less in the Sklansky PPA. These faster three-operand adders can be utilized for three-operand multiplication in image processing applications and Internet of Things (IoT) security systems.

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques

Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an ‘error’ signal used to dynamically regulate the chip’s operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6 V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.

Transient responses of double core-holes generation in all-attosecond pump-probe spectroscopy

Double core-holes (DCHs) show remarkable and sensitive effects for understanding electron correlations and coherence. With advanced modulation of x-ray free-electron laser (XFEL) facility, we propose the forthcoming all-attosecond XFEL pump-probe spectroscopy can decipher the hidden photon-initiated dynamics of DCHs. The benchmark case of neon is investigated, and norm-nonconserving Monte-Carlo wavefunction method simulates non-Hermitian dynamics among vast states, which shows superiority in efficiency and reliability. In our scheme, population transfer to DCHs is sequentially irradiated by pump and probe laser. By varying time delay, Stark shifts and quantum path interference of resonant lines sensitively emerge at specific interval of two pulses. These ubiquitous multi-channel effects are also observed in phase-fluctuating pulses, derived from extra phases of impulsive Raman processes by pump laser. Non-perturbation absorption/emission verifies the uniquely interchangeable role of two pules in higher intensity. Our results reveal sensitive and robust responses on pulse parameters, which show potential capacity for XFEL attosecond pulse diagnosis and further attosecond-timescale chemical analysis.

Thermally programmable time delay switches for multi-step assays in paper-based microfluidics

Paper-based microfluidic devices offer advantages such as low cost and disposability for point-of-care diagnostic applications. However, actuation of fluids on paper can be a challenge in multi-step and complex assays. In this work, a thermally programmable time-delay switch (TPTDS) is presented which operates by causing delays in the fluid path of a microfluidics paper-based analytical device (μPAD) by utilizing screen-printed wax micro-bridges. The time-delay is achieved through an electrical power feedback loop which indirectly adjusts the temperature of each individual micro-bridge, melting the wax into the paper. The melted wax manipulates the fluid flow depending on its penetration depth into the paper channel, which is a function of the applied temperature. To demonstrate functionality of the proposed method, the TPTDS is employed to automate and perform the nitrate assay which requires sequential delivery of reagents. Colorimetric detection is used to quantify the results by utilizing an electronic color sensor.

Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines.

Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)-based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.

Multi-Frequency Channel Measurement and Characteristic Analysis in Forested Scenario for Emergency Rescue

Wireless communication has been widely used in emergency rescue, including from command vehicles to command vehicles, command vehicles to rescue teams, command vehicles to wireless sensors, and rescue teams to intelligent platforms such as unmanned vehicles. Compared to those used in cities and suburbs, when the same communication equipment is used in forests, its communication performance, such as transmission distance, is entirely different. The main reason for this phenomenon is the extraordinary complexity of wireless signal propagation in forest scenarios. Therefore, in order to accurately and quantitatively describe the wireless channel characteristics in forest scenarios, a frequency channel measurement activity is conducted in a forest and analysis is performed to acquire the channel characteristics in forest scenarios. The measurements are carried out at 380 MHz, 640 MHz, and 1420 MHz in virgin forest. Based on the measurement data, the average power delay profile (APDP) is obtained, and multipath components (MPCs) are extracted. Root mean square (RMS) delay spread and path loss (PL) are analyzed according to MPCs. Furthermore, a new path loss model is proposed. Finally, a new path loss model and relative analysis are provided.

Finding the longest delay paths for the array-form multipliers using a genetic algorithm

Traditional digital multipliers are often designed in array forms or other variants. Timing of array-form multipliers can be analyzed by static timing analysis (STA), but the obtained timing result is conservative and pessimistic. Although statistical static timing analysis (SSTA) can partly solve the pessimism, it still does not generate test patterns for those near-to-longest delay paths. Finding near-to-longest delay paths can be helpful to designing error tolerant circuits, with which aggressive timing (with timing violation) can be exploited. In such design scenarios one should find test vectors to activate those near-to-longest delay paths in order to further run SPICE-precision diagnose on those potential timing violating critical paths. Test vector generation for such a testing problem is essentially an exhaustive enumeration problem when dealing with different forms of array multipliers. However, large size multipliers would result in an extremely large enumeration space for finding the longest delay path (LDP) test vectors. Currently there is no deterministic method that can guarantee to find test vectors for exact LDPs of a large size multiplier. Only very few research papers have addressed this problem, proposals are limited to heuristic methods without guarantee of finding the LDPs with the testing vectors. This paper investigates the potential of a genetic algorithm (GA) for searching the extensive test pattern space. By a fine design of GA, experimental running shows that a combination of well tuned evolutionary operators does empower the possibility of finding the LDPs for a set of moderate size carry-save adders (CSA) multipliers with the wordlength (WL) up to 25 bits on a plain laptop computer. Statistical properties of the proposed GA are examined.

An initial investigation of the non-isotropic feature of GNSS tropospheric delay

Tropospheric delay is a significant error source in Global Navigation Satellite Systems (GNSS) positioning. Slant Path Delay (SPD) is commonly derived by multiplying Zenith Tropospheric Delay (ZTD) with a mapping function. However, mapping functions, assuming atmospheric isotropy, restrict the accuracy of derived SPDs. To improve the accuracy, a horizontal gradient correction is introduced to account for azimuth-dependent SPD variations, treating the atmosphere as anisotropic. This study uncovers that, amidst atmospheric dynamics and spatiotemporal changes in moisture content, the SPD deviates from that based on traditional isotropy or anisotropy assumption. It innovatively introduces the concept that SPD exhibits non-isotropy with respect to azimuth angles. Hypothesis validation involves assessing SPD accuracy using three mapping functions at five International GNSS Service (IGS) stations, referencing the SPD with the ray-tracing method. It subsequently evaluates the SPD accuracy with horizontal gradient correction based on Vienna Mapping Function 3 (VMF3) estimation. Lastly, the non-isotropic of SPD is analyzed through the ray-tracing method. The results indicate the smallest residual (1.1–82.7 mm) between the SPDs with VMF3 and those with the ray-tracing. However, introducing horizontal gradient correction yields no significant improvement of SPD accuracy. Considering potential decimeter-level differences in SPD due to non-isotropic tropospheric delay across azimuth angles, a precise grasp and summary of these variations is pivotal for accurate tropospheric delay modeling. This finding provides vital support for future high-precision tropospheric delay modeling.

CASTELO: Convex Approximation based Solution To Elliptic Localization with Outliers

This short communication considers mitigating the negative effects of possibly unreliable path delay measurements acquired in non-line-of-sight (NLOS) environments on the positioning performance, a problem deserving further investigation within the expanding research area of elliptic localization. We present CASTELO, a Convex Approximation based Solution To Elliptic Localization with Outliers, to achieve such a goal. Our proposal corresponds to a mixed semidefinite (SD)/second-order cone (SOC) programming formulation derived from an error-mitigated nonlinear least squares (LS) location estimator, presenting itself as a remedy for the neglect of positivity of NLOS biases suffered by the majority of currently fashionable outlier-handling approaches. In terms of analytical discussions, we provide rationales supporting the incorporation of the SOC constraints, which serve to tighten the problem obtained after SD relaxation, and conduct a complexity analysis for the ultimate mixed SD/SOC programming formulation. Simulations are carried out to confirm the strong ability of CASTELO to attain reliable elliptic localization in the presence of NLOS outliers.

A Novel Adaptive ANC Algorithm for Removal of Background Noise in Speech Applications

Noise is an unsafe mechanical toxin that causes serious hearing misfortune in the working environment of every nation. The working people in the military, mining, development, printing, and saw factories tend to lose their hearing performance due to the adverse effects of noise generated by the machines. They undergo elevated levels of noise, with various machinery producing greater levels of noise measured in decibels. These sounds may cause major health problems that may not allow the person to work in such conditions. Algorithms like Least Mean Square (LMS), Normalized Least Mean Squared (NLMS), Filtered-x Least Mean Squared (FxLMS) and Filtered-x Normalized Least Mean Squared (FxNLMS) are frequently being used for noise cancellation. Moreover, these filters have instability and poor noise reduction; slow convergence also requires a greater number of filter taps and less performance to identify the unknown system in the Active Noise Canceller (ANC). In this paper, a Précised FxNLMS (P-FxNLMS) algorithm is introduced for an ANC. This algorithm consists of dual adaptive filters, an updated Variable Step Size (VSS), a delay in the primary path, a slight improvement in the on-line secondary path, and a modified filter step size when compared to an existing ANC system, with the purpose of minimizing the demerits of existing algorithms. Initially, the P-FxNLMS algorithm was tested with Additive White Gaussian Noise (AWGN) and later tested with real noises from the NOISEUS dataset to check the noise reduction performance. The increase in Signal to Noise Ratio (SNR) segmentation for P-FxNLMS is around 1.45 dB to 4.07 dB and 38.46 % to 73.68 % of the Mean Square Error (MSE) as compared to the algorithms available for different sounds with different SNR input levels. From the performance results of MSE and SNR improvement (SNRi), we found improvements compared with existing algorithms

Characteristic Analysis and Modeling of Train‐to‐Train Wireless Channel in Station Scenario

In this paper, ray tracing (RT) is used to analyze the characteristics of train‐to‐train (T2T) wireless channel in 2.1 GHz frequency band, including path loss, multipath clustering, delay spread, Rice factor, angular spread, and channel nonstationarity. It is found that the change of environment has a great influence on the characteristics of the wireless channel, which not only causes the birth and death of multipath clusters but also makes the channel appear nonstationary characteristics. In order to characterize the nonstationarity of the T2T wireless channel, we introduce the time correlation coefficient (TPCC) of the power delay profile (PDP), analyze the nonstationarity of the T2T wireless channel, and give the quasi‐stationarity distance. The results are basically consistent with the measured data.

A novel multipath QUIC protocol with minimized flow complete time for internet content distribution

The rapid growth of network services and applications has led to an exponential increase in data flows on the internet. Given the dynamic nature of data traffic in the realm of internet content distribution, traditional TCP/IP network systems often struggle to guarantee reliable network resource utilization and management. The recent advancement of the Quick UDP Internet Connect (QUIC) protocol equips media transfer applications with essential features, including structured flowcontrolled streams, quick connection establishment, and seamless network path migration. These features are vital for ensuring the efficiency and reliability of network performance and resource utilization, especially when network hosts transmit data flows over end-to-end paths between two endpoints. QUIC greatly improves media transfer performance by reducing both connection setup time and transmission latency. However, it is still constrained by the limitations of single-path bandwidth capacity and its variability. To address this inherent limitation, recent research has delved into the concept of multipath QUIC, which utilizes multiple network paths to transmit data flows concurrently. The benefits of multipath QUIC are twofold: it boosts the overall bandwidth capacity and mitigates flow congestion issues that might plague individual paths. However, many previous studies have depended on basic scheduling policies, like round-robin or shortest-time-first, to distribute data transmission across multiple paths. These policies often overlook the subtle characteristics of network paths, leading to increased link congestion and transmission costs. In this paper, we introduce a novel multipath QUIC strategy aimed at minimizing flow completion time while taking into account both path delay and packet loss rate. Experimental results demonstrate the superiority of our proposed method compared to standard QUIC, Lowest-RTT-First (LRF) QUIC, and Pluginized QUIC schemes. The relative performance underscores the efficacy of our design in achieving efficient and reliable data transfer in real-world scenarios using the Mininet simulator.

Digit-Serial DA-Based Fixed-Point RNNs: A Unified Approach for Enhancing Architectural Efficiency.

The next crucial step in artificial intelligence involves integrating neural network models into embedded and mobile systems. This requires designing compact and energy-efficient neural network models in silicon for optimized performance. This article introduces a unified approach for enhancing the architectural efficiency of long short-term memory (LSTM) recurrent neural networks (RNNs). Precisely, two new structures (I and II) based on the two's complement (TC) digit-serial distributed arithmetic (DSDA) technique are presented. The block-circulant matrix-vector multiplications (MVMs) and element-wise multiplications (EWMs) are formulated using TC DSDA. In addition, a fixed-point (FxP) training procedure for quantized LSTM RNNs is considered and validated for speech recognition tasks. Both structures leverage the circular rotation of weights and generate partial products with input digit slices. A new partial-product generator (PPG) and partial-product selector (PPS) designed to work with both unsigned and signed digits is introduced. In Structure I, a nonpipelined MVM is realized with a few PPGs and PPSs, followed by a shift-accumulate unit (SAU). Conversely, in Structure II, a suitably chosen depth-pipelined MVM is achieved with multiple PPGs and PPSs, followed by a shift-to-add tree (SAT). A critical path delay (CPD) analysis for both the proposed structures is also presented. Compared with previous works, post-synthesis results on 28 -nm fully depleted silicon-on-insulator (FDSOI) technology reveal that for a model size of 128 × 128 , Structures I and II provide 39.87% , 95.63% , and 30.95% , 91.18% more area and energy efficiencies, respectively.