Pass Gate Research Articles

FinFET SRAM Optimization With Fin Thickness and Surface Orientation

In this paper, the design space, including fin thickness <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(T_{\rm fin})$ </tex></formula> , fin height <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(H_{\rm fin})$</tex></formula> , fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints. The simulation results, which consider the variations of both <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$T_{\rm fin}$</tex></formula> and threshold voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm th})$</tex></formula> , show that most FinFET SRAM configurations achieve a superior read/write noise margin when compared with planar SRAMs. However, when two fins are used as pass gate transistors (PG) in FinFET SRAMs, enormous array dynamic energy is required due to the increased effective gate and drain capacitance. On the other hand, a FinFET SRAM with a one-fin PG in the (110) plane shows a smaller write noise margin than the planar SRAM. Thus, the one-fin PG in the (100) plane is suitable for FinFET SRAM design. The one-fin PG FinFET SRAM with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$T_{\rm fin} = \hbox{10}\ \hbox{nm}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$H_{\rm fin} = \hbox{40}\ \hbox{nm}$</tex></formula> in the (100) plane achieves a three times larger noise margin when compared with the planar SRAM and consumes a 17% smaller bit-line toggling array energy at a cost of a 22% larger word-line toggling energy. It also achieves a 2.3 times smaller read delay and a 30% smaller write delay when compared with the planar SRAM.

A Bendable-Channel FinFET for Logic Application

Bendable-channel fin field-effect transistor (FET) (FinFET) (BC-FinFET) is presented for the basic logic family that includes nand, nor , and pass gate. The BC-FinFET can replace the suspended-gate FET (SGFET), and its function is very similar to that of a double-gate MOSFET. The BC-FinFET is composed of an n-type and p-type MOSFETs, and hence, it can be applicable for logic circuits. Numerical simulations based on elementary characteristics extracted from the fabricated BC-FinFET have been carried out for nand and nor circuits from an input-output characteristics' point of view. The proposed architecture can improve the standby and dynamic power consumption by reduction of the number of SGFETs and the size of the chip, while improving circuit performance.

Highly Reliable SRAM Circuit Technology Using FinFETs

This paper introduces a flex-pass-gate SRAM (Flex-PG SRAM), which is a FinFET-based SRAM to enhance both the read and write margins independently. The flip-flop in the Flex-PG SRAM consists of usual FinFETs, while the pass gates consist of double-"independent"-gate FinFETs, i.e., "four-terminal"- (4T-) FinFETs. By optimizing the current drivability in the 4T-FinFET pass gates according to operational conditions of read and write, both the read and write margins are enhanced. TCAD simulations revealed that the Flex-PG SRAM increases the read margin by 71 mV without the cell size penalty and decrease in the write margin, even when its 6σ tolerance is ensured. Also, a fabricated device proved its feasibility.

LOW POWER, LOW LATENCY, HIGH THROUGHPUT 16-BIT CSA ADDER USING NONCLOCKED PASS-TRANSISTOR LOGIC

As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming major obstacles for circuit design in the nanoscale technologies. Due to increased density of transistors in integrated circuits and higher frequencies of operation, power consumption, propagation delay, PDP, and area is reaching the lower limits. We have designed 16-bit adder circuit by Carry-Select Adder (CSA) using different pass-transistor logic. The adder cells are designed by DSCH3 CAD tools and layout are generated by Microwind 3 VLSI CAD tools. Using CSA technique, the power dissipation, PDP, area, transistor count, are calculated from the layout cell of proposed 16-bit adder for Ultra Deep Submicron feature size of 120, 90, 70, and 50 nm. The UDSM signal parameters are calculated such as signal to noise ratio (SNR), energy per instruction (EPI), Latency, and throughput using layout parameter analysis of BSIM 4. The simulated results show that the CPL is dominant in terms of power dissipation, propagation delay, PDP, and area among the other pass gate logics. Our CPL circuit dominates in terms of EPI, SNR, throughput, and latency in signal parameters analysis. The proposed CPL adder circuit is compared with reported results and found that our CPL circuit gives better performance.

Design Implications of Single Event Transients in a Commercial 45 nm SOI Device Technology

This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets.

Flex-pass-gate SRAM for static noise margin enhancement using FinFET-based technology

We propose a flex-pass-gate SRAM (Flex-PG SRAM), which is a FinFET-based SRAM to enhance both the read and write margins independently. The flip-flop in the Flex-PG SRAM consists of usual FinFETs, while its pass gates consist of double-“independent”-gate FinFETs, i.e., “four-terminal”- (4T-) FinFETs. A 4T-FinFET has a variable threshold voltage controlled by the second gate voltage. This function enables the Flex-PG SRAM to optimize the current drivability in the pass gates according to operational conditions of read and write. This results in enhancement of both the read and write margins. TCAD simulations revealed that the Flex-PG SRAM increases the read margin by 71mV without the cell size penalty and decrease in the write margin, even when its 6σ tolerance is ensured. Also, a half-cell experiment proved its feasibility.

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

Immediate soft error detection using pass gate logic for content addressable memory

Content addressable memory (CAM) is used in many applications. As the process technology scales into the deep sub-micron regime, soft error rate increases significantly. Densely integrated memory cells in CAM are prone to soft errors. Bit flipping in CAM leads to an incorrect search operation which could be fatal from a system point of view. The proposed scheme enables the detection of soft errors immediately and the correction of problems with small additional logic gates.

Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS

This paper presents a 4-b low-power, low-voltage flash analog-to-digital converter (ADC). The proposed ADC is pipelined and mainly consists of three stages: 1) track-and-hold (T/H); 2)differential comparator; and 3) differential cascode voltage switch with pass gates (DCVSPG) encoder. The T/H uses a current-mode dual-array structure to reduce the aperture jitter for high-input signal frequency. The differential comparator eliminates the use of the resistor ladder circuit by generating the reference voltages internally. The DCVSPG encoder has a full output signal swing and compact logic design style of pass gate circuits, which makes it suitable for high sampling frequency. The DCVSPG encoder reduces the power consumption by a factor of 88% as compared with the conventional ROM encoder. The ADC is designed in 130-nm CMOS technology. Fast Fourier transform tests prove proper operation of the ADC sampled at 2.5 GHz for the input signal frequency up to 1 GHz

A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates

Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause a large overhead in area when a number of contexts are used. To overcome the overhead, a fine-grained MC-FPGA architecture using a floating-gate-MOS functional pass gate (FGFP) is presented which merges threshold operation and storage function on a single floating-gate MOS transistor. The test chip is designed using a 0.35 μm CMOS-EPROM technology. The transistor count of the proposed multi-context switch (MC-switch) is reduced to 13% in comparison with SRAM-based one. The total area of the proposed MC-FPGA is reduced to about 56% of that of a conventional SRAM-based MC-FPGA.

Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 µm dual gate oxide CMOS technology.

SOI MOSFET structure with a junction-type body contact for suppression of pass gate leakage

A SOI MOSFET structure with a junction-type body contact [body-junctioned-to-gate (BJG)] is proposed to effectively suppress the parasitic bipolar effect in all kinds of MOSFETs including the pass transistor, which can be realized with compact design and simple processes. It utilizes the buried contact process to minimize the area consumption. Various on-chip test circuits have been fabricated to verify the BJG characteristics and it is shown that the proposed structure provides nearly perfect immunity against the circuit failure caused by the parasitic bipolar effect and an excellent speed performance, so that it can be a promising candidate for the SOI circuits.

A dynamic-threshold SOI device with a J-FET embedded source structure and a merged body-bias-control transistor. II. Circuit simulation

For pt.I see ibid., vol. 47, no.8, p.1587-92 (2000). A primary transistor having an embedded J-FET, or resistor, immediately under the source junction and a small subsidiary body-bias-control transistor enables the construction of a variable-threshold SOI MOSFET with a small area penalty and without any limitation on the power-supply voltage. The subsidiary transistor, synchronized with the gate input signal, injects charges into the body depending on the output-node transient condition and controls the body potential to increase the on-current and decrease the off-current. The embedded J-FET eliminates such floating-body effects as delay hysteresis. The inverter delay time with a 1-pF load capacitance can be shortened to 40% of that of a bulk device under I-V operation, A different embedded J-FET circuit construction under the source enables an NMOS pass gate to be constructed without the output-amplitude degradation caused by the source follower, with a switching speed higher than that of a conventional CMOS pass gate.

Modified super pass gate for multiple-valued logic circuits

A model of a super pass gate (SPG) is adapted to allow multiple-valued logic circuit connections and designs that are normally prohibited by the formal synthesis and minimisation technique for the device. The modification of the SPG allows more efficient circuit minimisation to be achieved for functions that do not readily reduce under the formal synthesis technique.

Memory Chips with Adjustable Configurations

In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories to achieve this flexibility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and Wmax⁡ can be constructed with the extra cost of Wmax⁡ – 1 pass gates, (Wmax⁡/2) 2-to-1 multiplexers, and ⌈log⁡2[log⁡2(k) + 1]⌉ mode pins. A novel scheme to overlap the address pins with mode control pins and achieve the mode control with only one extra pin is also presented. The paper discusses the architecture of the proposed VaWiRAMs in detail, analyzes the design tradeoffs and introduces the concept of FPMCAs.

Transient measurements of SOI body contact effectiveness

A technique for characterizing the effectiveness of SOI MOSFET body contacts under transient conditions, by measuring the transient lateral bipolar current in a SOI pass gate, is demonstrated. Using this technique, the minimum rise or fall edge rate required to guarantee that the body potential over the device width follows the contact potential is defined. While this technique is applied specifically to a Schottky body tie, it can be generalized to other technologies and other body ties.

Fully-depleted SOI CMOS for analog applications

Fully-depleted (FD) SOI MOSFETs offer near-ideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFETs at high temperature or at gigahertz frequencies is outlined as well.

CMOS-process-independent average power dissipation macromodelling

An accurate CMOS-process-independent average power dissipation macromodel is presented for the inverter and multiple input macros, including NAND, NOR, the transmission gate, pass gate and SRAM cell. A new macro activity time period is defined and accurate macro activity estimations are achieved without the need for analogue propagation delay simulation.

A single chip parallel multiplier by MOS technology

A parallel multiplier design based on the five-counter cell is discussed. A design optimization for the performance in speed is proposed at the logic design level which is developed into an MOS circuit design. The comparison of the five-counter cell design and the full adder cell design reveals that the proposed design is most useful with pass gate logic and results in high-speed multiplication (approximately twice as fast as that of the full adder design) with a moderate increase in hardware complexity. With the five-counter design, an improvement in the hardware complexity of a squarer can be expected. >