Abstract
In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories to achieve this flexibility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and Wmax can be constructed with the extra cost of Wmax – 1 pass gates, (Wmax/2) 2-to-1 multiplexers, and ⌈log2[log2(k) + 1]⌉ mode pins. A novel scheme to overlap the address pins with mode control pins and achieve the mode control with only one extra pin is also presented. The paper discusses the architecture of the proposed VaWiRAMs in detail, analyzes the design tradeoffs and introduces the concept of FPMCAs.
Highlights
Designing efficient memory systems for modern microprocessors is increasingly becoming a challenge [10, 12, 15, 18, 19,21]
We presented the design of a variable width RAM called VaWiRAM which allows the user to configure the RAM to the desirable width
A VaWiRAM chip reconfigurable between widths and Wma can be constructed at an additional cost of Wmax- pass gates, (Wmax/2) 2-to-1 multiplexers, and logz[logz(k)+ 1] mode pins
Summary
Designing efficient memory systems for modern microprocessors is increasingly becoming a challenge [10, 12, 15, 18, 19,21]. We present the design of a variable width RAM (VaWiRAM) that can be programmed to configure itself to variable widths. By changing the values on a few control pins, the chips can be reprogrammed to different configurations Another fact motivating the research in this paper is that different processors need different interface logic in order to be able to use the same memory chip. The primary objective of this paper is to present the design of a variable width RAM (VaWiRAM) which can be configured to different widths. A second objective of this paper is to present the design of a fully programmable memory cell array (FPMCA) with programmable logic on the chip, enabling to interface the memory module to various processors, with reduced parts count.
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