Pass Gate Transistor Research Articles

Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this article. Increased bitline (BL) resistance in sub-10 nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an increased leakage current of half-selected bitcells on BL and BL capacitance operated in high frequency. In a realistic write operation, BL parasitics also cause 30% SRAM yield loss in interconnect resistance-dominated technology nodes. Thus, this proposed method analyzes the time-dependent impacts of BL parasitic resistors, capacitors, and pass-gate (PG) transistors on write margin considering the negative BL (NBL) assist technique.

A Study of the Correlation between Word-Line Resistance, Gamma Ratio and Write Failure in SRAM

Based on the technical needs of customers and users, semiconductor devices have been advanced for the last a few decades. Most of customers and users prefer to have a faster speed and a longer usage time for their electronic devices (e.g., smartphone, tablet PC, and wearable devices). Those needs must have been the de-facto driving force for scaling down the physical dimension of transistors in integrated circuit (IC). When it comes to develop advanced transistors with faster speed but lower power consumption, there should exist conflicting electrical characteristics. For example, as the feature size of transistors in IC chip has been aggressively scaled down, the metal line resistance in IC has become a key knob in determining the aforementioned conflicting electrical characteristics, when the metal lines are designed to be densely placed and structured in a very limited chip area. If the metal line structure is less immune to heat dissipation from transistors, the performance of transistors should be degraded. Since a high speed operation for application processor (AP) is demanded by chip designers, the performance of static random access memory (SRAM) has become more critical. This is because the total volume of SRAM in AP has gradually been increasing. In this thesis, it turned out that the degraded gamma ratio (i.e., the ratio of the on-state drive current of pass-gate transistor to the on-state drive current of pull-up transistor) of failed bit-cells in SRAM array was the main reason for write failure. In addition, it was observed that the Word Line (W/L) sheet resistance of the failed cell is higher than that of good cells. We found that the gamma ratio become smaller when the W/L resistance is high (which is originated from a thinner metal line by metal etch test). We have set up an in-house failure model, in which a high-W/L-resistance-induced W/L enables a signal delay, and thereby, the write margin of SRAM is degraded. Therefore, the performance of pass-gate transistor with a higher WL resistance has become slower than that of normal transistor. To enhance the gamma ratio, we have developed a metal etch recipe. This can tune for reducing the deviation in the distribution of gamma ratio, and therefore, raise up the mean value of gamma ratio by optimizing the PMOS performance. As a result, the gamma ratio was improved from 1.1 to 1.2, and we can completely secure the strong stability of bit-cell without any write failure. And we have used a new index to manage the SRAM write failure, i.e., a Gamma of RWL Index. This would be useful for predicting the write failure of SRAM in real time in FAB. In industry, the index is standardized internally, and we are expecting that this newly-developed index would become significant in managing various FAB parameters. Figure 1

NCFET-Based 6-T SRAM: Yield Estimation Based on Variation-Aware Sensitivity

The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS) < 60 mV/decade at 300 K. In this work, the n-type NCFET (i.e., pull-down (PD) and passgate (PG) transistor in six-transistor (6T) SRAM bit-cell) has SS of 53.92 mV/decade, and the p-type NCFET (i.e., pull-up (PU) transistor in the 6T SRAM bit-cell) has SS of 58.96 mV/decade. In the NCFET-based SRAM cell (vs. conventional SRAM cell with conventional planar bulk MOSFETs), its read (hold)-stability and write-ability are evaluated by the metric of read static noise margin (SNM) and write-ability current (Iw), respectively. Then, under process-induced random variation, sensitivities of SNM and Iw are extracted. Finally, the yield of NCFET-based SRAM array (vs. conventional SRAM array) is quantitatively estimated using the cell-sigma.

Ambipolar SB-FinFETs: A New Path to Ultra-Compact Sub-10 nm Logic Circuits

Ultracompact sub-10-nm logic gates based on ambipolar characteristics of Schottky-barrier (SB) FinFETs and gate workfunction engineering (WFE) approach are introduced. Novel logic gate designs are proposed using WFE, whereby adjustment of workfunction in the contacts as well as two independently biased FinFET gates leads to an unprecedented degree of freedom for logic functionality that has not been explored before. The use of SB contacts, along with the high-k gate dielectric and ultrathin body, bestows a high-degree of short-channel immunity to the SB-FinFETs with ambipolar current–voltage characteristics down to 5 nm. The unique trait of the proposed novel logic gates is to lower CMOS transistor count by 50% and hence reduce overall area and power dissipation significantly. To illustrate this potential, an entirely novel conjugate (n/p channel) CMOS pass-gate transistor that can function as a two-transistor (2T) XOR and minimalist 2T NAND/NOR gates is designed and verified with TCAD simulations. Depending on the gate designed, TCAD simulations indicate that judicious choice of gate workfunctions between 3.7 and 5.2 eV can lead to CMOS logic gates with a power–delay product (PDP) at ${5}\times {10}^{-{18}}$ J level with immunity to ±0.1-eV workfunction variations. It is shown that WFE in independent-gate SB-FinFETs can lead to ultracompact logic circuits with 50% reduction in area and up to 10 times reduction in power, without significant degradation to overall PDP performance due to slower switching response compared with the conventional designs with p-n junction FinFET counterparts.

Reliability and Energy Efficiency of the Tunneling Transistor-Based 6T SRAM Cell in Sub-10 nm Domain

The static random access memory (SRAM) has a significant impact on the overall power consumption and energy efficiency of any micro and nanoelectronics application or system. SRAM consumes a considerable amount of power in the idle state. As a consequence, the leakage power is one of the most critical metrics in SRAM designs. This brief evaluates the standby leakage power in the tunnel FET (TFET)-based 6T SRAM cell for different pull-up, pull-down, and pass-gate transistors ratios (PU: PD: PG) and compared to 10-nm FinFET-based 6T SRAM designs. It is observed that the 10-nm TFET-based SRAMs have 60.7, 65.22, and 59.7 times less standby leakage power compared to the 10-nm FinFET-based SRAMs when the PU: PD: PG ratios are 1:1:1, 1:5:2, and 2:5:2, respectively. This brief also presents an analysis of the stability and reliability of TFET-based 6T SRAM circuit with a reduced supply voltage of 500 mV. The static noise margin, which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T TFET SRAM cell. The robustness of the optimized TFET-based 6T SRAM circuit is also evaluated at different supply voltages. Simulations were done in HSPICE and cadence tools.

Static fault localization of subtle metallization defects using near infrared photon emission microscopy

In this paper, two electroluminescence phenomena, which enabled the static electrical fault localization of subtle back-end-of-line metallization defects using near-infrared photon emission microscopy in the logic circuitry and the memory array, are described. In the logic circuitry, through the study of the defect-induced hot carrier emissions from the combinational logic gates, distinctive differences in emission characteristic between open and short defects are identified. Using this defect induced emission characterization approach, together with layout trace and analysis, the type of defect can be predicted. The defect physical location, which yielded no detectable hotspot signal, can also be narrowed down along the long failure net. This allows for the selection of the most appropriate physical failure analysis approach for defect viewing and thus achieving significant reduction in failure analysis cycle time. In the memory array, the weak emission from partially turned-on pass gate transistor is leveraged to localize marginal opens and shorts on the wordline node of the pass-gate transistor. These approaches are applied with great success in the foundry environment to localize yield limiting defects that resulted in SCAN and memory build-in self-test failure, without memory bitmap, diagnostic support or measurable IDD leakage, on advanced technology nodes devices. A discussion on the factors that influence the success rate of this approach is also provided.

Analysis of TID Process, Geometry, and Bias Condition Dependence in 14-nm FinFETs and Implications for RF and SRAM Performance

Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- $V_{\textit {th}}$ transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and $V_{\textit {th}}$ , while the low- $V_{\textit {th}}$ transistors exhibit a larger change in off-state leakage current. The “ worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( $V_{\textit {gs}}=V_{\textit {dd}}$ ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- $V_{\textit {th}}$ transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.

Effective Drive Current for Pass-Gate Transistors

A two-point expression of effective drive current ( $I_{\rm eff\_{}PG})$ for pass-gate (PG) transistors is proposed for the first time. We demonstrate that the proposed expression of $I_{\rm eff\_{}PG}$ estimates the PG latency with a reasonable accuracy (relative error $I_{\rm eff\_{}PG}$ provides a simple yet efficient approach for technology evaluation and projection for PG heavy applications such as field-programmable gate array routing. We also show that the previously proposed static CMOS effective drive current ( $I_{\rm eff\_{}inv})$ is not a valid figure of merit when applied to PG transistors, because PG transistors operate in a different regime from the transistors in CMOS inverters. The scaling trend of $I_{\rm eff\_{}PG}$ is discussed, which illustrates the $I_{\rm eff\_{}PG}$ does not improve from device scaling as much as CMOS saturation current ( $I_{{\mathrm{dsat}}})$ and effective drive current ( $I_{\rm eff\_{}inv})$ do.

SRAM cell with asymmetric pass‐gate nMOSFETs for embedded memory applications

A novel asymmetric static RAM (SRAM) cell is fabricated on planar silicon-on-insulator CMOS technology, in which pass-gate (PG) transistors are asymmetric. Since lightly doped drain structure of PG transistors use only gate-to-source, this cell improves read stability by 43% when compared with the conventional SRAM 6T symmetric cell. Additionally, cell-leakage current reduces by 24% also due to the PG transistor gate-to-drain underlap design. Although it needs more current to write data to storage node, but no more voltage is needed based on measurements. The novel cell is still suitable for embedded memory.

Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation

A near-threshold voltage ( $V_{{\rm {th}}}$ ) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super- $V_{{\rm {th}}}$ operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near- $V_{{\rm {th}}}$ region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near- $V_{{\rm {th}}}$ region. This paper proposes a read buffer with adjusted the number of fins or $V_{{\rm {th}}}$ to resolve the problems in the near- $V_{{\rm {th}}}$ region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near- $V_{{\rm {th}}}$ region.

A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy

A post-process carrier injection scheme for 6T-SRAM is proposed. The proposed scheme pinpoints and simultaneously repairs only cells that have low read disturb margin by injecting electrons to the strong pass gate transistor. Compared with the conventional electron injection scheme that injects electrons to either side of the pass gate transistor of all cells, the proposed scheme achieves 57% less BL delay, 31% less read energy, 32 ~ 256 times shorter injection time and 3% area reduction. The concept is validated with 2, 64, 128 kb SRAM in 40 nm standard CMOS process. Experiments show around 40 mV operation margin increase after the proposed injection.

Comparison of SRAM Cells for 10-nm SOI FinFETs Under Process and Environmental Variations

We explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write margin, and leakage for future 10-nm FinFETs. Process variations are based on the ITRS and modeled at device (TCAD) level. We propose a method to incorporate them into a BSIM-CMG model card for time-efficient simulation. We analyze cells with different fin numbers, supply voltages, and temperatures. Results show a 1.8× improvement of RSNM for 8T SRAM cells, the need for stronger pull-downs to secure read stability in 6Ts, and high leakage sensitivity to temperature (10× between 40°C and 100°C). As a specific example, we show how the RSNM of a 6T SRAM cell can be improved by using back-gate biasing techniques for independent-gate FinFETs. We show how WLMN is increased by reducing the strength of pull-up transistors when reverse back-gate biasing is applied on it and how the RSNM can be increased by reducing the strength of access transistor by reverse back-gate biasing of pass-gate transistors. When combining these two techniques, RSNM can be improved up to 25% without compromising cell write ability for any sample. In general, when compared to previous technologies, read stability is untouched, writeability is reduced, and leakage keeps stable.

Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM

A statistical threshold voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> shift variation of the pass gate (PG) transistor in local electron injected asymmetric PG transistor 6T-SRAM is investigated. Measurements show that the positive correlation between the PG transistor <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> shift ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THPG</sub> shift) and its original <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> of the PG transistor ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THPG</sub> ) before injection due to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD</i> effect is self-compensated by the negative correlation between those by <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ID</i> effect. As a result, the measured <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THPG</sub> shift is less correlated with the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THPG</sub> before electron injection. Therefore, near <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> word-line (WL) voltage injection self-convergence scheme is proposed to avoid <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THPG</sub> shift in the high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THPG</sub> cell and enhance in the low <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THPG</sub> cell. By the proposed scheme, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD</i> effect is reduced and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ID</i> effect is enhanced. The improved negative correlation factor is observed between the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THPG</sub> shift and the forward <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THPG</sub> before injection. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is increased by 21 times by the proposed scheme. As a result, excess write margin degradation is suppressed. Furthermore, the fabricated 64 kb SRAM macro demonstrates 3 times larger WL operation voltage window, 41% less read margin variation and 80 mV lower <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CCMIN</sub> after the local electron injection.

A Correlative Analysis Between Characteristics of FinFETs and SRAM Performance

A correlation between the characteristics of the 30-nm <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LG</i> fin-shaped field-effect transistors and the static random-access memory performance is precisely studied. By investigating an effect of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variation to the static noise margin (SNM) variation of two different memory states of the storage node, it is revealed that the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variations of the pull-up, pull-down, and pass-gate transistors correlate with the SNM. Moreover, the contribution and the severity of each transistor variation to σSNM are clarified.

Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor

Three types of electron injection scheme: both side injection scheme and self-repair one side injection scheme Type A (injection for once) and Type B (injection for twice) are proposed and analyzed comprehensively for 65nm technology node 6T- and 8T-SRAM cells to find the optimum injection scheme and cell architecture. It is found that the read speed degrades by as much as 6.3 times in the 6T-SRAM with the local injected electrons. However, the read speed of the 8T-SRAM cell does not degrade because the read port is separated from the write pass gate transistors. Furthermore, the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb and write characteristics. The worst cell characteristics of Type A and Type B self-repair one side injection schemes were found to be the same. In the self-repair one side injection 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed schemes have no process or area penalty compared with the standard CMOS-process.

Improvement of Read Margin and Its Distribution by $V_{\rm TH}$ Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric pass gate transistor by post-process local electron injection is proposed. Local electron injection is automatically and simultaneously achieved to either pass gate transistor that most increases the read margin for each cell without investigating its characteristics. The proposed asymmetric VTH shift is twice as large as the conventional scheme without process and cell area penalty. Measurement results show 20% increase in SNM without write degradation by the asymmetric PG transistor. The proposed scheme also enhances the minimum read margin by 70% while reducing read margin distribution by 20%, thanks to the self-repair function.

Asymmetric Independent-Gate MOSFET SRAM for High Stability

In this paper, the application of an asymmetric independent-gate MOSFET (IG-MOSFET) to the bit-cell structures of the SRAM schemes that were previously proposed using the symmetric IG-MOSFET is analyzed. In addition, a novel SRAM scheme with the asymmetric IG-MOSFET is proposed to improve read stability and writeability by controlling the back gates of pass-gate and pull-up transistors. New array architecture is also suggested to prevent read stability degradation in the half-selected cell, where word line is selected but bit line is unselected. The previous SRAMs with IG-MOSFET (IG-SRAMs) fail to simultaneously improve read stability and writeability compared to the SRAM with the tied-gate MOSFET. The proposed IG-SRAM significantly improves both read stability and writeability at the cost of slightly increased bit-cell area and read delay, as compared to the previous IG-SRAMs.

FinFET SRAM Optimization With Fin Thickness and Surface Orientation

In this paper, the design space, including fin thickness <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(T_{\rm fin})$ </tex></formula> , fin height <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(H_{\rm fin})$</tex></formula> , fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints. The simulation results, which consider the variations of both <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$T_{\rm fin}$</tex></formula> and threshold voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm th})$</tex></formula> , show that most FinFET SRAM configurations achieve a superior read/write noise margin when compared with planar SRAMs. However, when two fins are used as pass gate transistors (PG) in FinFET SRAMs, enormous array dynamic energy is required due to the increased effective gate and drain capacitance. On the other hand, a FinFET SRAM with a one-fin PG in the (110) plane shows a smaller write noise margin than the planar SRAM. Thus, the one-fin PG in the (100) plane is suitable for FinFET SRAM design. The one-fin PG FinFET SRAM with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$T_{\rm fin} = \hbox{10}\ \hbox{nm}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$H_{\rm fin} = \hbox{40}\ \hbox{nm}$</tex></formula> in the (100) plane achieves a three times larger noise margin when compared with the planar SRAM and consumes a 17% smaller bit-line toggling array energy at a cost of a 22% larger word-line toggling energy. It also achieves a 2.3 times smaller read delay and a 30% smaller write delay when compared with the planar SRAM.

Static Noise Margin of Ultrathin-Body SOI Subthreshold SRAM Cells—An Assessment Based on Analytical Solutions of Poisson's Equation

This paper investigates the static noise margin (SNM) of ultrathin-body (UTB) SOI SRAM 6T/8T cells operating in the subthreshold region using analytical solutions of Poisson's equation validated with TCAD simulations. An analytical framework to calculate the SNM for UTB SOI SRAMs operating in the subthreshold region is presented. Our results indicate that for improving both read SNM (RSNM) and write SNM (WSNM), the back-gating technique is more effective in the subthreshold region than in the superthreshold region. The 6T UTB SOI subthreshold SRAM cell with the back-gating technique by increasing the strength of the pull-up transistors and decreasing the strength of the pass-gate transistors shows comparable RSNM with the 10T bulk subthreshold SRAM and an improvement in RSNM variation. Due to better electrostatic integrity, the back-gating technique (pull-up transistors with positive back-gate bias, pull-down/pass-gate transistors with negative back-gate bias) mitigates the 6T UTB SOI SRAM RSNM variation significantly with some improvement in RSNM. Increasing cell beta-ratio shows a limited improvement on RSNM and has no benefit on the SNM variability for the subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2times larger than the 6T SRAM cell in the subthreshold region. Both negative bit-line voltage (VBL) and boosted word-line voltage (VWL) are more effective than lower cell supply voltage to improve WSNM, and negative VBL shows a larger improvement in WSNM than boosted VWL.

Measurements and extractions of parasitic capacitances in ulsi layouts

This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts. It is well known that, in integrated circuits, the signal delay due to interconnects is comparable to that of gates. This aspect becomes particularly important, for example, during the design of clock trees in high-speed applications. In general, capacitance extraction is carried out with software tools but they should be validated on a set of geometrical structures, which have been accurately characterized and that are representative of the circuit layouts. Experimental characterization of these structures and their set up in a golden set of measures is still a challenging task. In this paper, we first describe some experimental approaches to measure capacitances of structures from the golden set and in particular we identify a high accuracy transducer based on pass-gate transistors. We then propose a software implementation of the floating random walk algorithm that solves the drawbacks in the extraction of capacitances of interconnects in a nonhomogeneous medium as an industrial layout. Finally, experimental and simulation results are presented, validating the adopted approach.