Effective Drive Current for Pass-Gate Transistors

Abstract

A two-point expression of effective drive current ( $I_{\rm eff\_{}PG})$ for pass-gate (PG) transistors is proposed for the first time. We demonstrate that the proposed expression of $I_{\rm eff\_{}PG}$ estimates the PG latency with a reasonable accuracy (relative error $I_{\rm eff\_{}PG}$ provides a simple yet efficient approach for technology evaluation and projection for PG heavy applications such as field-programmable gate array routing. We also show that the previously proposed static CMOS effective drive current ( $I_{\rm eff\_{}inv})$ is not a valid figure of merit when applied to PG transistors, because PG transistors operate in a different regime from the transistors in CMOS inverters. The scaling trend of $I_{\rm eff\_{}PG}$ is discussed, which illustrates the $I_{\rm eff\_{}PG}$ does not improve from device scaling as much as CMOS saturation current ( $I_{{\mathrm{dsat}}})$ and effective drive current ( $I_{\rm eff\_{}inv})$ do.