Partial Reconfiguration Research Articles

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq

New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.

Technical Implementation of Dual Mode Fault Tolerance

Field Programmable Gate Array (FPGA) is susceptible from hazardous radiation that leads to be in error state. In order to avoid that condition, we apply a fault tolerance technique. Most of the fault tolerances today are only using one mode, mean the fault tolerance that is applied will run all of the time without any changing its design. It is neglect about the condition, when the hazard radiation will occur more frequently or not. As researches have shown that in the orbit, the radiation hazard, which is happening frequently in the South Atlantic Anomaly (SAA). Therefore, in this project creates a new methodology in implementation of fault tolerance by using dual mode, when radiation is happened frequent we apply more robust fault tolerance, if not frequent we apply by simple fault tolerance. A robust fault tolerance will use more resources and simple fault tolerance will use less resources. Configuration in FPGA is done by Dynamic Partial Reconfiguration (DPR) means the transition from robust to simple fault tolerance or vice versa is done while the system is running. In this paper will talk about the technical implementation of dual mode fault tolerance, by presenting systematically order and important aspect to get success in implementing the design. The paper shows a result that dual mode fault tolerance can be configured in FPGA successfully

Dynamic Partial Reconfiguration Implementation of AES Algorithm

This work reports Partial Reconfiguration (PR) by which selected areas of an FPGA can be reconfigured during runtime. Today cryptographic algorithms are not safe also embedded cryptographic hardware is costly. Hence to make it cost effective and to provide more secureness reconfigurable hardware such as FPGA is used with the concept of partial reconfiguration. This work gives briefings about the method of hardware implementation for AES encryption algorithm with Dynamic reconfigurable keys. Our implementation reaches very good efficiencies than the compared one as we have adopted our own methodology for key expansion. With the combination of adopted methodology & used FPGA this paper shows better agreement as compared to previous work. This implementation could be a good solution to preserve confidentiality and convenience to the information in the numeric communication.

Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs

The rapid adoption of FPGA-based systems in space and avionics demands dependability rules from the design to the layout phases to protect against radiation effects. Triple Modular Redundancy is a widely used fault tolerance methodology to protect circuits against radiation-induced Single Event Upsets implemented on SRAM-based FPGAs. The accumulation of SEUs in the configuration memory can cause the TMR replicas to fail, requiring a periodic write-back of the configuration bit-stream. The associated system downtime due to scrubbing and the probability of simultaneous failures of two TMR domains are increasing with growing device densities. We propose a methodology to reduce the recovery time of TMR circuits with increased resilience to Cross-Domain Errors. Our methodology consists of an automated tool-flow for fine-grain error detection, error flags convergence and non-overlapping domain placement. The fine-grain error detection logic identifies the faulty domain using gate-level functions while the error flag convergence logic reduces the overwhelming number of flag signals. The non-overlapping placement enables selective domain reconfiguration and greatly reduces the number of Cross-Domain Errors. Our results demonstrate an evident reduction of the recovery time due to fast error detection time and selective partial reconfiguration of faulty domains. Moreover, the methodology drastically reduces Cross-Domain Errors in Look-Up Tables and routing resources. The improvements in recovery time and fault tolerance are achieved at an area overhead of a single LUT per majority voter in TMR circuits.

FPGA Evaluation of Reconfigurable Modules With Fault Detection and Repair Technique

<p>This paper proposes a fault detection and repair algorithm which is suitable for fault free reconfigurable systems. In recent years Built in Self Repair digital systems have got very important role in the applications such as nuclear systems, space missions and communication systems etc where system reliability is very critical . Systems designed to operate in critical conditions will collapse due to even a single fault occurrence. To avoid these situations many methods have developed in recent years. This work proposes an area efficient and fast fault detection and repair algorithm. For the evaluation of the new approach and older methods a system with a standalone module and four add on modules were designed and evaluated for resource utilization using XUPV5 board. The entire FPGA is divided in to tiles and each module is implemented in different tiles using partial reconfiguration method using Xilinx Plan Ahead 14.2 with partial reconfiguration facility.</p>

Partial Reconfigurable Implementation of IEEE802.11g OFDM

Today’s mobile networks are moving towards creating base stations and mobile stations that are compatible with many standards simultaneously. One way of achieving it is to reconfigure and time multiplex the processing resources based on the present necessity. Field Programmable Gate Arrays have become one of the best choices for implementing digital signal processing and Software Defined Radio platforms due to advancements in VLSI over the past few decades. Partial Reconfiguration has regained its importance in the last decade and is the one of the best methodologies to implement an Software Defined Radio. This paper presents an implementation of physical layer specifications of IEEE 802.11g using dynamic partial reconfiguration on FPGA. The Orthogonal Frequency Division Multiplexing (OFDM) Physical layer is implemented with various encoding and modulation schemes to achieve different data rates. The design has been implemented in Xilinx Virtex-5 board. Keywords: FPGA, IEEE 802.11g, OFDM, Partial Reconfiguration

Energy‐prediction scheduler for reconfigurable systems in energy‐harvesting environment

Energy harvesting has been demonstrated to be a promising approach to mitigating energy constraints. Unlike battery-based energy, available system energy significantly varies for energy-harvesting systems. Partial dynamic reconfiguration is adopted as an effective approach for accelerating wireless sensor network (WSN) applications. Although a reconfigurable system can achieve better performance compared with software implementation, reconfiguration potentially requires a large amount of energy and time, particularly for cases where reconfiguration occurs frequently. To address this issue, a novel weather-aware scheduler based on the weather-conditioned moving average (WCMA) prediction algorithm is proposed in this study. To demonstrate the authors approach, a heterogeneous reconfigurable node is also proposed. The implementation of the proposed approach can improve reconfigurable system performance by up to 50% under energy-harvesting conditions. The novelty of this work is 2-fold. First, a prototype is adopted to demonstrate its efficiency for WSN. Second, a novel scheduler is proposed to manage hardware reconfiguration. In the scheduler, WCMA is used to predict future harvested energy.

A Modeling Tool for Dynamically Reconfigurable Systems

In this paper, we suggest a tool dedicated to model systems that support the dynamic partial reconfiguration. The purpose of this tool is to provide an abstract view of the developed application. It facilitates the task of the designer by abstracting many low level details and design stages. The proposed tool enables the modeling of the application to be implemented by setting its different components and the constraints to be respected namely: reconfigurable modules, static modules, the link between the application modules, the constraints on the distribution of the area of Field-Programmable Gate Arrays (FPGA) etc. The information entered through a graphical interface of the tool will be used to generate the necessary data for Xilinx tools to pursue the various implementation stages of the dynamic partial reconfiguration technique

A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

Multidimensional Signaling and Coding Enabling Multi-Tb\/s Optical Transport and Networking: Multidimensional aspects of coded modulation

The design of next-generation optical transmission systems and networks should address the concerns with respect to a limited bandwidth of information infrastructure, high energy consumption, as well as the need to support the network heterogeneity and demand for an elastic and dynamic bandwidth allocation. To address these concerns simultaneously, we propose an adaptive, software-defined, low-density parity check (LDPC)-coded multiband approach that involves spatial-multiple-input, multiple-output (MIMO) and an all-optical orthogonal frequency-division multiplexing (OFDM) scheme since it can enable energy efficient high-bandwidth delivery with fine granularity and elastic model of bandwidth utilization. The modulation is based on multidimensional signaling to improve the tolerance to fiber nonlinearities and imperfect compensation of channel impairments and has a hybrid nature with both electrical and optical degrees of freedom employed. Optical degrees of freedom include spatial and polarization modes in optical fibers supporting spatial-division multiplexing (SDM), while electrical degrees of freedom are based on 2M orthogonal basis functions. The adaptive coding has been performed by partial reconfiguration of the corresponding parity-check matrix. The proposed scheme is suitable for the conveyance of the information over optical fibers with bit rates exceeding 10 Tb/s. At the same time, the multitude of degrees of freedom will enable finer granularity and elasticity of the bandwidth, the features essential for next generation networking.

TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network

Dynamic partial reconfiguration of FPGAs enables the dynamic specialization of the circuit for the runtime needs of the application. Previously a tool flow, called the TLUT tool flow, was developed to aid the designer in applying dynamic circuit specialization (DCS) for their designs. The TLUT tool flow generates an implementation in which the lookup tables (LUTs) can be specialized during runtime. In this paper, place and route algorithms are described for the TCON tool flow. The TCON tool flow generates implementations in which not only the logic infrastructure (LUTs) is dynamically specialized, but also the routing infrastructure of the FPGA. Exploiting the reconfigurability of the FPGA interconnection network further improves area (50% to 92% less LUTs and 36% to 81% less wiring), logic depth (a 63% to 80% reduction) and power consumption. To achieve this, major changes were needed, not only in the mapping, but also in the place and route steps. This work describes the altered place and route algorithms, called TPlace and Troute.

OCEAN, a flexible adaptive Network-On-Chip for dynamic applications

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement of applicatives tasks in reconfigurable zones. However, the dynamic management of the tasks impacts the communications since they are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various interconnection networks are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the OCEAN network that supports the communication constraints into the context of dynamic reconfigurations. Thanks to a generic platform allowing in situ characterizations of network performances, fair comparisons of various Networks-On-Chip can be realized. The FPGA and ASICs implementations of the OCEAN network are also discussed.

Power consumption models for the use of dynamic and partial reconfiguration

Minimizing the energy consumption and silicon area are usually two major challenges in the design of battery-powered embedded computing systems. Dynamic and Partial Reconfiguration (DPR) opens up promising prospects with the ability to reduce jointly performance and area of compute-intensive functions. However, partial reconfiguration management involves complex interactions making energy benefits very difficult to analyze. In particular, it is essential to realistically quantify the energy loss since the reconfiguration process itself introduces overheads. This paper addresses this topic and presents a detailed investigation of the power and energy costs associated to the different operations involved with the DPR capability. From actual measurements considering a Xilinx ICAP reconfiguration controller, results highlight other components involved in DPR power consumption, and lead to the proposition of three power models of different complexity and accuracy tradeoffs. Additionally, we illustrate the exploitation of these models to improve the analysis of DPR energy benefits in a realistic application example.

New approach to emulate SEU faults on SRAM based FPGAS

Field Programmable Gate Arrays (FPGAs) offer high capability in implementing of complex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets (SEUs). To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided. In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA. Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.

Platform design and imitative innovation inside the transition black-box: Korean nuclear power plant APR1400 case

This research focuses on a platform-design building momentum and an imitative innovation capability for the successful transition of a catch-up country into its post catch-up stage. Through the analysis of Korean nuclear power plant APR1400 development case with its specific process inside the transition black-box, APR1400 is proposed as a platform design with a common technological architecture that is indigenously established by Korea through a partial reconfiguration of the dominant design imported from leading countries. APR1400 has also been playing as a distinctive transition momentum for driving Korea into its post catch-up stage with various derivatives more concurrently, by providing Korea with the critically significant means of retrieving and reusing the existing knowledge rather diffusely accumulated during its catch-up stage into a more relevant one for transition.

Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques

In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration.

An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve

With the arrival of partial reconfiguration technology, modern FPGAs support tasks that can be loaded in (removed from) the FPGA individually without interrupting other tasks already running on the same FPGA. Many online task placement algorithms designed for such partially reconfigurable systems have been proposed to provide efficient and fast task placement. A new approach for online placement of modules on reconfigurable devices, by managing the free space using a run-length based representation. This representation allows the algorithm to insert or delete tasks quickly and also to calculate the fragmentation easily. In the proposed FPGA model, the CLBs are numbered according to reflected binary gray space filling curve model. The search algorithm will quickly identify a placement for the incoming task based on first fit mode or a fragmentation aware best fit mode. Simulation experiments indicate that the proposed techniques result in a low ratio of task rejection and high FPGA utilization compared to existing techniques.

GSM Based Configuration of FPGA

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by either the customer or a designer after manufacturing – hence “field-programmable”. In-flight reconfigurability and dynamic partial reconfiguration enhances space applications with re-programmable hardware and at runtime adaptive functionality attracts the use of FPGAs. FPGAs can provide designers with almost limitless flexibility, but once FPGA is programmed and interfaced with other pheripherals, it’s difficult to change the application which is running on FPGA. So, here we use a wireless programming technique to configure the FPGA based on our requirement. A wireless medium is preferred so as to avoid a physical connection with FPGA. In our idea we are going to select the application program in RAM and directly configuring it to FPGA using GSM. Hence we can swap from one application program to another by using a message sent from the user.

Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration

A Givens rotation based scalable QRD core which utilizes an efficient pipelined and unfolded 2D multiply and accumulate (MAC) based systolic array architecture with dynamic partial reconfiguration (DPR) capability is proposed. The square root and inverse square root operations in the Givens rotation algorithm are handled using a modified look-up table (LUT) based Newton-Raphson method, thereby reducing the area by 71% and latency by 50% while operating at a frequency 49% higher than the existing boundary cell architectures. The proposed architecture is implemented on Xilinx Virtex-6 FPGA for any real matrices of sizem×n, where4≤n≤8andm≥nby dynamically inserting or removing the partial modules. The evaluation results demonstrate a significant reduction in latency, area, and power as compared to other existing architectures. The functionality of the proposed core is evaluated for a variable length adaptive equalizer.

RUN TIME DYNAMIC PARTIAL RECONFIGURATION USING MICROBLAZE SOFT CORE PROCESSOR FOR DSP APPLICATIONS

DSP Application requires a fast computations & flex ibility of the design. Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. In this paper we are using mi croblaze soft core processor & ICAP Port to reconfi gure the FPGA at runtime. ICAP is accessed through a light-weight custom IP w hich requires bit stream length, go, and done signa l to interface to a system that provides partial bit stream data. The partial bit s tream is provided by the processor system by readin g the partial bit files from the compact flash card. Our targeted DSP application is matrix multiplication; we are reconfiguring design by changing partial modules at run time. To change the partial bit stream we in terfaces a microblaze Soft processor & using a UART interface.ISE13.1 & PlanAhead is used for partial reconfiguration of FP GA .EDK is used for microblaze soft processor desig n & ICAP Interface .The simulation is done using Chip Scope Logic Analyzer & the complete hardware implementation is done on X ilinx VIRTEX -6 ML605 Platform.