RUN TIME DYNAMIC PARTIAL RECONFIGURATION USING MICROBLAZE SOFT CORE PROCESSOR FOR DSP APPLICATIONS

Abstract

DSP Application requires a fast computations & flex ibility of the design. Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. In this paper we are using mi croblaze soft core processor & ICAP Port to reconfi gure the FPGA at runtime. ICAP is accessed through a light-weight custom IP w hich requires bit stream length, go, and done signa l to interface to a system that provides partial bit stream data. The partial bit s tream is provided by the processor system by readin g the partial bit files from the compact flash card. Our targeted DSP application is matrix multiplication; we are reconfiguring design by changing partial modules at run time. To change the partial bit stream we in terfaces a microblaze Soft processor & using a UART interface.ISE13.1 & PlanAhead is used for partial reconfiguration of FP GA .EDK is used for microblaze soft processor desig n & ICAP Interface .The simulation is done using Chip Scope Logic Analyzer & the complete hardware implementation is done on X ilinx VIRTEX -6 ML605 Platform.