Partial SOI Research Articles

High-Voltage 3-D Partial SOI Technology Platform for Power Integrated Circuits

A partial silicon on insulator (PSOI) is a widely recognized technology suitable for high-voltage (HV) architectures for power integrated circuits (PICs). Despite the added process complexity compared with SOI reduced surface field (RESURF), this technology offers a wider range of voltage ratings due to the action of the depletion layer in the handle wafer (HW), reduced parasitic capacitances due to the extra volume of the depletion region in the HW, and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-D designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of HV integrated circuits (HVICs) where low ON-state resistance and reduced self-heating are essential requirements. This work presents a PSOI technology platform with the voltage ratings ranging from 45 to 400 V while providing low ON-state resistance, good hot carrier injection stability, as well as electrostatic discharge (ESD) capability of the HV devices. For example, for a 375-V rated laterally diffused MOSFET (LDMOSFET),this technology achieves an ON-state resistance of 1435 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , an over 50% improvement compared with the state-of-the-art SOI technologies while maintaining competitive reliability.

A novel deep gate power MOSFET in partial SOI technology for achieving high breakdown voltage and low lattice temperature

A novel deep gate power MOSFET in partial SOI technology for achieving high breakdown voltage and low lattice temperature

Novel fast-switching LIGBT with P-buried layer and partial SOI* *Project supported by the National Basic Research Program of China (Grant No. 2015CB351906) and the Science Foundation for Distinguished Young Scholars of Shaanxi Province, China (Grant No. 2018JC-017).

A novel silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) is proposed in this paper. The proposed device has a P-type buried layer and a partial-SOI layer, which is called the BPSOI-LIGBT. Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer, the proposed structure generates two new peaks in the surface electric field distribution, which can achieve a smaller device size with a higher breakdown voltage. The smaller size of the device is beneficial to the fast switching. The simulation shows that under the same size, the breakdown voltage of the BPSOI LIGBT is 26% higher than that of the conventional partial-SOI LIGBT (PSOI LIGBT), and 84% higher than the traditional SOI LIGBT. When the forward voltage drop is 2.05 V, the turn-off time of the BPSOI LIGBT is 71% shorter than that of the traditional SOI LIGBT. Therefore, the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT. In addition, the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.

Simulating the Self-Heating Effect for MOSFETs with Various Configurations of Buried Oxide

SOI MOSFETs have the worst properties of heat removal from an active region, which negatively affects the reliability and efficiency of integrated circuits. Using TCAD modeling, we investigate the self-heating effect in the following structures of deeply submicron MOSFETs with different configurations of buried oxide: traditional bulk MOSFET, SOI structure, SELBOX structure, partial SOI structure, thin-BOX SOI structure, UTBB SOI structure, and quasi-SOI structure. It is shown that, for a number of new designs, the maximum temperature in the MOSFET structure is significantly reduced as compared to Тmax of the standard SOI MOSFET structure; it approaches the values typical of standard MOSFETs on bulk silicon.

Analytical model of buried air partial SOI LDMOS

A two-dimensional analytical model has been proposed for the Air Partial Silicon-On-Insulator (APSOI) LDMOS in this paper for the first time. The analytical solutions for the device are derived on the basis of the two-dimensional Poisson equation. An electric field modulation model that takes into account both the lateral and vertical electric field is proposed. The surface electric field is modulated through the variation of buried layer parameters with electric field modulation effect. Under the same simulation parameters, the breakdown voltage of APSOI LDMOS is 140% higher than that of traditional SOI and 93% higher than that of the traditional Silicon-On-Insulator structure with Step-Doped Drift region (SDDSOI). Also, it has been researched that the role of the key structural parameter in device performance is consistent with the expected results of the model, which proves that the effectiveness of electric field modulation effect and our model has guiding significance for device parameter optimization.

Dimension Effect on Breakdown Voltage of Partial SOI LDMOS

Dimension effect on breakdown voltage (BV) of lateral double-diffused metal-oxide–semiconductor field-effect transistor in partial silicon-on-insulator (PSOI) technology is comprehensively studied. The maximum BV (BVmax) is examined under various settings of the device length ${L}$ and the active silicon film thickness ${t}$ . It is shown that there exists an optimal pair of ( ${L}$ , ${t}$ ) for PSOI at which the highest BV can be achieved. The ratio of ${L}$ / ${t}$ is better chosen between 5 and 7 for the device designs, in particular, $L/t={\mathrm{ 6}}$ can be considered as the optimal one theoretically. Moreover, impacts of the silicon window length $L_{w}$ and the drift doping concentration $N_{dr}$ on the BV, the on-resistance ( $R_{\mathrm{ on}}$ ) and the figure-of-merit ( $=\!{\mathrm{ BV}}^{2}/R_{\mathrm{ on}}$ ) are also carefully studied.

A Reliable Nano Device with Appropriate Performance in High Temperatures

There are many problems during designing MOSFETs in nano scale regime. Some problems contain high gate current, high off current and high electron temperature. These problems are created when the peak of electric field is high which causes reducing the device reliability. So, reducing the peak of electric field can be an objective during designing a device. In this paper, a new structure for improvement of the partial SOI MOSFET parameters is presented. So, oxide layers are considered in the channel and in the extended drain region to reduce the peak of electric field. This reduction results in achieving reduced off current, gate current and electron temperature. The simulation with ATLAS simulator shows that the new structure has improved hot carrier effect and its reliability is more than conventional one.

A High-Voltage (&gt;600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology

A high-voltage lateral double-diffused MOSFET with N-island (NIS) and step-doped drift (SDD) region in partial silicon-on-insulator (PSOI) technology is proposed. In the lateral direction, the SDD region and the NIS on the buried oxide layer (BOX) introduce two additional electric field peaks, which can improve the surface field distribution and breakdown voltage (BV). In the vertical direction, due to the highly doped NIS, a higher electric field is induced into the BOX layer, which can achieve a higher vertical BV. As a consequence, the BV is enhanced significantly. Moreover, the NIS with a larger doping concentration can provide a higher current of the proposed device, and thus, the ON-resistance ( $R_{{\mathrm{\scriptscriptstyle ON}}})$ is reduced. The 2-D simulation results show that the BV of the proposed structure can achieve 680 V, and $R_{{\mathrm{\scriptscriptstyle ON}}}$ is reduced by 10.2% and 14.7% in comparison with the conventional PSOI and buried n-type layer PSOI, respectively.

Upper drift region double step partial SOI LDMOSFET: A novel device for enhancing breakdown voltage and output characteristics

A new LDMOSFET structure called upper drift region double step partial silicon on insulator (UDDS-PSOI) is proposed to enhance the breakdown voltage (BV) and output characteristics. The proposed structure contains two vertical steps in the top surface of the drift region. It is demonstrated that in the proposed structure, the lateral electric field distribution is modified by producing two additional electric field peaks, which decrease the common peaks near the drain and gate junctions. The electric field distribution in the drift region is modulated and that of the buried layer is enhanced by the two steps in the top surface of the drift region, thereby resulting in the enhancement of the BV. The effect of device parameters, such as the step height and length in the top surface of the drift region, the doping concentration in the drift region, and the buried oxide length and thickness, on the electric field distribution and the BV of the proposed structure is studied. Simulation results from two-dimensional ATLAS simulator show that the BV of the UDDS-PSOI structure is 120% and 220% higher than that of conventional partial SOI (C-PSOI) and conventional SOI (C-SOI) structures, respectively. Furthermore, the drain current of the UDDS-PSOI is 11% larger than the C-PSOI structure with a drain-source voltage VDS = 100 V and gate-source voltage VGS = 5 V. Simulation results show that Ron in the proposed structure is 74% and 48% of that in C-PSOI and C-SOI structures, respectively.

A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs.Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100μA), at drain–source voltage of VDS=100V and gate–source voltage of VGS=25V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87μA and 51μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

A 600V-Class Partial SOI LDMOS with Step-Doped Drift Region

A 600V-class lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) in partial silicon-on-insulator (PSOI) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped method induces an electric field peak in the surface of the device, which can reduce the surface field in the device and adjust the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance.

A novel partial SOI EDMOS (>800 V) with a buried N-type layer on the double step buried oxide

In this paper, a high voltage partial silicon-on-insulator (PSOI) extended drain metal–oxide–semiconductor (EDMOS) field effect transistor with a buried N-type layer (BNL) on the double-step buried oxide (DSBOX) is proposed. Due to the DSBOX, two additional peaks of the electric field are introduced in the drift region, modulating the electric field, achieving a more uniform distribution in the drift, and improving the lateral breakdown voltage (BV). The BNL provides a great population of positive charges on top of the DSBOX and enhances the electric field in the BOX, leading to a higher vertical BV. Moreover, the silicon window provides a thermal conduction path from the active region to the substrate, significantly alleviating the self-heating effect (SHE) in comparison to the conventional SOI-EDMOS (C-SOI).

Design of a 1200-V ultra-thin partial SOI LDMOS with n-type buried layer

A novel 1200-V ultra-thin partial silicon-on-insulator (PSOI) lateral double-diffusion metal oxide semiconductor (LDMOS) with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed in this paper. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conduction region for majority carriers and a silicon window to improve self-heating effect (SHE). A combination of uniform and linear variable doping (ULVD) profile is utilized in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (Ron,sp) and breakdown voltage (BV). With the n-drift region length of 80μm, the NBL PSOI LDMOS obtains a high BV of 1243V which is improved by around 105V in comparison to the conventional SOI LDMOS with linear variable doping (LVD) profile for the n-drift region (LVD SOI LDMOS). Besides, the 1200-V NBL PSOI LDMOS has a lower maximum temperature (Tmax) of 333K at a power (P) of 1mW/μm which is reduced by around 61K. Meanwhile, Ron,sp and Tmax of the NBL PSOI LDMOS are lower than those of the conventional LVD SOI LDMOS for a wide range of BV.

Analysis on the off-state design and characterization of LIGBTs in partial SOI technology

Classical high voltage devices fabricated on SOI substrates suffer from a backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes the off-state behavior of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrate. During the initial development stage the SJ LIGBT was found to have very high leakage. This was attributed to the back and side coupling effects. This paper discusses these effects and shows how this problem could be successfully addressed with minimal modifications of device layout. The off-state performance of the SJ LIGBT at different temperatures is assessed and a comparison to an equivalent LDMOSFET is given.

A novel partial-SOI LDMOSFET (>800 V) with n-type floating buried layer in substrate

In this paper, a novel high voltage lateral double diffused metal–oxide–semiconductor (LDMOS) field effect transistor based on partial silicon-on-insulator (PSOI) technology is proposed and investigated based on the numerical simulations. The structure is characterized by an n-type floating buried layer (NFBL) in the substrate under the silicon window near the drain. The buried layer in the substrate modulates the lateral and vertical electric field, which results in the electric field of the drift region distributed uniformly. Therefore, the breakdown voltage (BV) of the device is significantly improved. The influences of the key parameters on device performance of the proposed structure are discussed. Moreover, the self-heating effect (SHE) is greatly alleviated duo to the silicon window helps thermal conduction to the substrate, which improved the reliability of device application.

Uniform and linear variable doping ultra‐thin PSOI LDMOS with n‐type buried layer

A novel ultra-thin partial silicon-on-insulator (PSOI) LDMOS with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conductivity region for majority carriers to significantly improve the self-heating effect. A combination of uniform and linear variable doping (LVD) profile with highly initial concentration is utilised in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (R on,sp) and breakdown voltage (BV), as well as achieving low power dissipation. With a 60-µm n-drift region length, the NBL PSOI LDMOS obtains a high BV of 940 V with a low maximum temperature (T max) of 327 K at a power (P) of 1 mW/μm, which is reduced by around 56 K in comparison to the conventional SOI LDMOS using an LVD profile for the n-drift region (LVD SOI LDMOS). Moreover, R on,sp of the NBL PSOI LDMOS is lower than that of the LVD SOI LDMOS for a wide range of BV from 400 to 900 V.

Thin-film LDMOS on partial SOI with improved breakdown voltage and suppressed kink effect

Thin-film (TF) lateral double-diffused metal-oxide-semiconductor field effect transistor (LDMOSFET or LDMOS) of small dimensions on partial silicon-on-insulator (PSOI) with improved breakdown voltage and suppressed kink effect is introduced and studied. The silicon window and field plate can modulate the surface electric field of silicon film and, thus, their design parameters can be adjusted to achieve optimal breakdown voltage. Moreover, the silicon window can also provide a conduction path from the thin silicon film to the substrate and prevent hole accumulation in the floating body of silicon-on-insulator (SOI) devices, which can consequently suppress the kink effect. Effects of the device parameters (e.g. location of the field plate, location of silicon window, and doping concentrations of the drift region, silicon window and substrate) that control the performance of TF PSOI LDMOS are carefully studied. Compared with the conventional TF SOI LDMOS of small dimensions, the simulation results show that this proposed TF PSOI LDMOS exhibits approximately 100% improvement on the breakdown voltage and entirely eliminates the kink effect.

Injected charges in partial SOI LDMOSFETs: A new technique for improving the breakdown voltage

High breakdown voltage and reduced on-resistance are desired characteristics in power MOSFETs. In order to obtain an excellent performance of lateral double-diffused MOSFET (LDMOS) devices, we have proposed a new technique in which at the surface of buried oxide, negative and positive charges are incorporated, periodically. This strategy modulates the electric field and causes high breakdown voltage. Also, by considering the charges at interface of the buried oxide, depletion islands form in the drift region that the current density increases on the top of the drift region and the on-resistance decreases. Our simulation with two-dimensional ATLAS simulator shows that an Injected Charge in Buried Oxide of Partial SOI LDMOSFET (ICBO-PSOI) has considerable improvement in high frequency with reduced switching delay.

200-V Lateral Superjunction LIGBT on Partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an Rdson of 765 mΩ·mm2. It exhibits half the value of specific on-state resistance Rdson and three times higher saturation current (Idsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in Rdson at 175 °C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process.

A Novel High-Voltage ($&gt;$ 600 V) LDMOSFET With Buried N-Layer in Partial SOI Technology

A novel lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with a buried N-type layer (BNL) in partial silicon-on-insulator (PSOI) is introduced to achieve breakdown voltage (BV) above 600 V and reduce on-resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ). The BNL induces enhanced voltage into the buried oxide layer, which results in higher BV. The higher doping concentration in the BNL can provide more electrons to support higher current and thus reduce on-resistance. The proposed LDMOS transistor with a BNL in PSOI (BNL-PSOI) is analyzed and compared with LDMOS transistors with conventional SOI (CSOI), conventional PSOI (CPSOI), and a BNL in SOI (BNL-SOI) by 2-D numerical simulations. The results indicate that the proposed structure can significantly improve BV up to 660 V and reduce on-resistance by 13.6%-15.5% in comparison to CSOI and CPSOI.