Upper drift region double step partial SOI LDMOSFET: A novel device for enhancing breakdown voltage and output characteristics

Abstract

A new LDMOSFET structure called upper drift region double step partial silicon on insulator (UDDS-PSOI) is proposed to enhance the breakdown voltage (BV) and output characteristics. The proposed structure contains two vertical steps in the top surface of the drift region. It is demonstrated that in the proposed structure, the lateral electric field distribution is modified by producing two additional electric field peaks, which decrease the common peaks near the drain and gate junctions. The electric field distribution in the drift region is modulated and that of the buried layer is enhanced by the two steps in the top surface of the drift region, thereby resulting in the enhancement of the BV. The effect of device parameters, such as the step height and length in the top surface of the drift region, the doping concentration in the drift region, and the buried oxide length and thickness, on the electric field distribution and the BV of the proposed structure is studied. Simulation results from two-dimensional ATLAS simulator show that the BV of the UDDS-PSOI structure is 120% and 220% higher than that of conventional partial SOI (C-PSOI) and conventional SOI (C-SOI) structures, respectively. Furthermore, the drain current of the UDDS-PSOI is 11% larger than the C-PSOI structure with a drain-source voltage VDS = 100 V and gate-source voltage VGS = 5 V. Simulation results show that Ron in the proposed structure is 74% and 48% of that in C-PSOI and C-SOI structures, respectively.