Partial SOI Research Articles

A new partial SOI power device structure with P-type buried layer

A new BPSOI (buried layer partial SOI) structure is developed, in which the P-type buried layer is implanted into the P − substrate by silicon window underneath the source of the conventional PSOI. The mechanism of breakdown is that the additional electric field produced by P-type buried layer charges modulates surface electric field, which decreases drastically the electric field peaks near the drain and source junctions. Moreover, the on-resistance of BPSOI is decreased as a result of increasing drift region doping due to neutralism of P-type buried layer. The results indicate that the breakdown voltage of BPSOI is increased by 52–58% and the on-resistance is decreased by 45–48% in comparison to conventional PSOI in virtue of 2-D numerical simulations using MEDICI.

Partial SOI type isolation for improvement of DRAM cell transistor characteristics

A new DRAM cell transistor using an isotropic etching under the storage node is proposed, and it is shown that the structure gives improvement both in the short-channel effect and in the body-bias control. The asymmetrical characteristics of the structure are analyzed by experiments and simulation, and the feasibility of utilizing the asymmetric characteristics is reported.

Realizing high breakdown voltages (>600 V) in partial SOI technology

A combination of uniform and variation in lateral doping (UVLD) profiles is proposed for the drift region of lateral power devices in partial SOI (PSOI) technology in order to achieve breakdown voltages above 600 V. LDMOS transistor structures incorporating the proposed doping profile are analyzed for their electrical characteristics and compared with conventional uniformly doped PSOI and thin layer SOI by extensive 2-D numerical simulations using MEDICI. The results indicate that the proposed doping profile can significantly improve the trade-off between breakdown voltage and specific on-resistance as well as the heat dissipation in comparison to uniformly doped PSOI and thin layer VLD SOI.

Thermally induced stress in partial SOI structure during high temperature processing

The thermally induced stresses in partial silicon-on-insulator (SOI) structures generated due to high temperature processing were simulated using finite element method in this work. By employing the Box-Behnken design for the response surface method, statistical models were established to relate the computational stresses to the structural geometric parameters, including oxide length (and width), oxide thickness and work layer thickness. With these statistical models, the geometrical parameters of the structure could be optimized to effectively reduce the thermally induced stresses in the partial SOI structures. In contrast to the full SOI wafer, withdrawal velocity is not the key parameter in determining the stress induced in the structure, but rather furnace temperature and structural parameters are the key parameters. It is found that thinner buried oxide is desired to reduce the stresses in the structure, and the length and width of the buried oxide should be above 60 μm for the induced stresses not to be excessive.

Simulation of nonequilibrium thermal effects in power LDMOS transistors

The present work considers electrothermal simulation of LDMOS devices and associated nonequilibrium effects. Simulations have been performed on three kinds of LDMOS: bulk Si, partial SOI and full SOI. Differences between equilibrium and nonequilibrium modeling approaches are examined. The extent and significance of thermal nonequilibrium is determined from phonon temperature distributions obtained using a common electronic solution and three different heating models (Joule heating, electron/lattice scattering, phonon scattering). The results indicate that, under similar operating conditions, nonequilibrium behavior is more significant in the case of full SOI devices, where the extent of nonequilibrium is estimated to be twice that of the partial SOI device and four times that of the bulk device. Time development of acoustic phonon and lattice temperatures in the electrically active region indicates that nonequilibrium effects are significant for times less than 10 ns.

Analytical modelling for the RESURF effect in JI and SOI power devices

The authors present a review and assessment of state-of-the-art analytical models which describe the breakdown behaviour of JI and SOI RESURF power devices. The results are compared with numerical values, and a short evaluation of strengths and weaknesses specific to each model is given. A new modelling concept for the breakdown regime in RESURF power structures is introduced, and the results are assessed against numerical values. The same technique can be used to derive the breakdown voltage of RESURF devices fabricated in JI and SOI technologies, and is potentially useful for non-standard technologies, such as linearly graded SOI, partial SOI and 3-D RESURF. The model provides accurate description for punch-through, non-punch-through and volume breakdown.

The integration of high-side and low-side LIGBTs on partial silicon-on-insulator

Partial silicon-on-insulator (PSOI) is a new technology for fabricating power integrated circuits (PICs) in which the buried oxide is patterned to give silicon windows beneath the anodes of the power devices, yielding breakdown voltages and a self-heating effect comparable to those obtained in bulk silicon, yet while retaining the good isolation between the power devices and the low-power CMOS which is inherent in silicon-on-insulator [Popescu A, Udrea F, Milne W. Proceedings of CAS. 1997. p. 102–3; Lim H, Udrea F, Garner D, Milne W. Solid-State Electronics 1999;43(7):1267–80]. For a PIC, both a high-side and a low-side power device are often required. While this is possible when the power devices are LDMOSFETs [Lim H, Udrea D, Garner K, Shen K, Milne W. Proceedings of CAS. 1999. p. 149–52], high-side Lateral Insulated Gate Bipolar Transistors (LIGBTs) are difficult to fabricate in PSOI due to the unacceptably high leakage current which flows from the anodes of the LIGBTs, through the silicon window, to the substrate, and which can constitute 9.3% of the total device current. In this article, we present a novel method of eliminating that current by incorporating a deep n + diffusion between the anode of the high-side LIGBT and the silicon window. Therefore, a PSOI PIC technology is arrived at, which has everything that is required for a PIC technology: a high breakdown voltage, a similarly good self-heating effect to bulk technology, a good turn-off performance, good isolation between power devices and CMOS circuitry, and the availability of both high-side and low-side LIGBTs and LDMOSFETs.

Modelling of self-heating effect in thin SOI and Partial SOI LDMOS power devices

This paper presents a comprehensive 2-D and 1-D study of the self-heating effect in thin Silicon-on-Insulator (SOI) and Partial SOI LDMOS power devices. A simple 1-D self-heating model based on a PSPICE RC thermal circuit which accounts for the temperature rise in on-state, transient and short-circuit conditions is developed. Unlike previous 1-D modelling attempts for SOI devices, our model takes into account the feedback effect of the local device temperature on the thermal conductivity and specific heat through an equivalent electrical RC network consisting of voltage controlled resistors and capacitors. The 1-D model is thoroughly assessed against extensive 2-D thermal simulations performed using the SILVACO-ATLAS device simulator and the results indicate an excellent agreement in all operating conditions. Furthermore, an accurate comparison between the thin SOI and Partial SOI devices is carried out.

Lateral insulated gate bipolar transistor(LIGBT) structure based on partial isolation SOI technology

A new LIGBT structure based on partial isolation SOI technology is proposed and demonstrated through numerical simulations. In comparison with conventional SOI LIGBTs, the new structure offers an enhanced RESURF (REduced SURface Field) effect and improved heat dissipation with no compromise in the switching speed and on-state resistance.

Intelligent Power IC with Partial SOI Structure

In the integration of power devices and control circuits, temperature rise caused by the heat dissipation of power devices and electric interference between power devices and control circuits are important problems. In this report, the following was demonstrated by using the partial silicon-on-insulator (SOI) structure with shielding layers. The partial SOI structure has the Si directly bonded areas where power devices are formed and SOI areas where control circuits are formed. Firstly, the temperature rise was reduced to about a half that in the complete SOI structure, and the latch-up occurrence in the control circuit was prevented by the insertion of shielding layers. Secondly, at the condition of 150° C and 16 V, the normal operation of an intelligent power IC consisting of multichannel power devices and a 1-bit microcomputer was accomplished.

Partial-SOI isolation structure for reduced bipolar transistor parasitics

A bipolar isolation structure with the capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>