Partial Product Reduction Research Articles

A Low-Power High-Accuracy Approximate Multiplier Using High-Order Approximate Compressors

To address the need to reduce power consumption, approximate multipliers have emerged as a potential solution for fault-tolerant applications. In this work, we present a new 8x8 approximate multiplier that focuses on minimizing performance while maintaining a high degree of accuracy. The design features two key features: firstly, based on their importance, different weights are handled by the compressors with different levels of precision, allowing for a trade-off between energy efficiency and minimum error. Second, higher order approximation compressors such as 8:2 compressors are used for intermediate weights to simplify the drive chain logic. This is, to our knowledge, the first design to successfully integrate higher-order approximate compressors into an approximate multiplier. Compared to a precision multiplier such as the Dadda tree multiplier, experimental results show that the proposed design offers significant energy savings while maintaining high accuracy. Key Words:- Approximate computing; Arithmetic circuits; Logic design; Low-power design; Partial Product reduction

Design and Analysis of Optimized Approximate Multiplier Using Novel Higher-Order Compressor

The energy-efficient error-tolerant circuits have paved the way for a whole new area in low-power consumption applications with approximate computing. The approximate computing fulfills the trade-off requirement of exact computation and provides efficient performance. In this paper, a novel energy-efficient multiplier has been proposed for image processing applications. In the multiplication process, compressors are used as an important component for the reduction of partial products. Higher-order approximate 5:2 and 6:2 compressors are also designed and simulated in VIVADO using Verilog coding. The proposed higher-order compressors result in less area and low-power consumption in comparison with the existing state-of-the-art technique. These high-performance compressors are used at the multipliers’ reduction stage, resulting in an energy-efficient circuit for error-tolerant applications. All the simulations were carried out in VIVADO considering 8-bit inputs. Multiplication performance shows 37.77 % (8-bit) improvement in terms of power consumption in comparison to the conventional multiplier. The multiplication process has been done on the original, negative, and sharpened images using their masks. The proposed multiplier shows 51.36% (original image), 6.04% (negative image), and 22.44% (sharpened image) PSNR improvement in comparison to state-of-the-art work.

An optimized design of delay-and energy-efficient Booth multiplier

Multipliers are essential computation units in virtually all computing systems, including processors and numerous AI accelerator architectures. This paper presents an optimized architecture for a Booth multiplier, targeting high performance while minimizing energy consumption and area utilization. The design optimization focuses on all three multiplier stages: partial product generation, reduction, and summation. To enhance delay and energy efficiency in the partial product generation stage, we first employed a simplified configuration comprising inverters and a sign selection unit instead of complex binary-to-two's complement circuitry. Next, to achieve further delay and area efficiency at this stage, logic optimization is applied at the partial product's generation circuitry by designing Booth encoders to remove redundant logic in multiplexers circuitry. Moreover, we introduced specialized sign compressors tailored for carry-save compression in the compression stage. Compared to conventional counterparts, these compressors offered lower power consumption and reduced critical path delay with only two XOR logic gates. Finally, in the summation stage, we proposed an optimized design segment for Carry Look-Ahead Adder for the final summation stage, designed to deliver swift throughput with minimal fan-in logic gates, even in the context of high bit-width configurations. This segment is cascaded to make a 13-bit final adder for the summation stage in the proposed design. The proposed architecture undergoes ASIC-targeted synthesis in Cadence Genus employing FreePDK CMOS 45 nm process technology. Synthesized results, along with theoretical design complexity comparison, demonstrate that the proposed design surpasses state-of-the-art 8 × 8 multiplier designs by critical metrics, including delay, power consumption, area utilization, power delay product, and area delay product.

Hybrid Radix-16 booth encoding and rounding-based approximate Karatsuba multiplier for fast Fourier transform computation in biomedical signal processing application

Multiplication is an essential biomedical signal processing function implemented in the Digital Signal Processing (DSP) cores. To enhance the speed, area and energy efficiency of DSP cores, approximate multiplication is used. Also, low power multiplier unit design is one of the requirements of DSP processor to meet the increasing demands. To balance both the design and error metrics of a multiplier design, an efficient Hybrid Radix-16 Booth Encoding and rounding-based approximate Karatsuba Multiplier (RBEKM-16) is proposed. This research introduces an Approximate Karatsuba multiplier based on rounding, utilizing rounding approximation to compute the least significant part of the product. Simple operators, like adders and multiplexers, replace complex and costly conventional Floating-Point (FP) multipliers in this process. Radix-4 logarithms are incorporated to further minimize hardware complexity and calculate the product's most significant part. Subsequently, an approximate 4-2 compressor is applied in the partial product reduction stage to generate the most significant bit result. In the experimental scenario, the efficiency of the multiplier is evaluated in terms of energy efficiency, area utilization and error rate by using Xilinx ISE 8.1i tool. The results from the experiments indicate that the suggested multiplier demonstrates improved energy efficiency, utilizes space more effectively, and performs well in applications related to biomedical signal processing. Further, the accomplished area utilization of the proposed 16-bit multiplier is 1068 μm2, delay is 3.01 ns, power consumption is 0.021 mW and power delay product is 119 fJ.

Exact Computing Multiplier Design using 5-to-3 Counters for Image Processing

This work presents a novel approach to improve the area and energy efficiency of 5:3 counter, a key element used in digital arithmetic. To provide an effective substitute for addition operations, mostly in the partial product reduction stage of larger multipliers, this study suggests a new 5:3 counter. The Input Shuffling Unit (ISU) is employed within the proposed 5:3 counter to minimize gate-level implementation and path delay during partial product reduction in 16-bit and larger multipliers, thereby enhancing area and energy efficiency. Consequently, there are 84% fewer choices of input-output combinations, thereby decreasing the circuit complexity with respect to area and energy usage. When compared to its existing counterparts, the suggested 5:3 compressor improves area utilization and energy usage by an average of 11%, 17%, and 17% in 8-, 16-, and 32-bit multipliers, respectively. The results of simulations demonstrate the superiority of our method over traditional designs, providing an increase in both area and energy efficiency. These results highlight the applicability and scalability of our method, which is appropriate for a variety of applications such as embedded systems and digital signal processing.

Performance optimized approximate multiplier architecture ST-AxM - based on statistical analysis and static compensation

In this study, our primary aim is to develop a highly efficient multiplier architecture tailored for approximate computing, with a specific focus on optimizing power efficiency. Multiplication constitutes a fundamental operation in computing, profoundly impacting applications ranging from signal processing to artificial intelligence. The emerging paradigm of approximate computing seeks to enhance hardware design by balancing computational accuracy with power consumption. Our objective is to achieve this balance by implementing a novel multiplier architecture employing several key methods. We aim to harness a smart and adaptable partial product reduction technique grounded in statistical analysis to reduce adder usage, incorporate power-efficient adder structures, and introduce static error compensation mechanisms to maintain lower error levels. Our methodology involves analyzing various multiplier hardware architectures, developing the proposed approximate multiplier architecture, and rigorously validating its performance against a state-of-the-art truncation multiplier. We utilize Xilinx ISE for synthesis to obtain results pertaining to area efficiency and power efficiency. Furthermore, we employ error metrics to comprehensively compare the performance of our proposed architecture with existing designs. Finally, we assess the practical applicability of these different multipliers by integrating them into an image sharpening application and evaluating metrics such as Peak Signal to Noise Ratio (PSNR) and Similarity Index (SI). Our results indicate that the statically truncated approximate multiplier outperforms existing designs by being 18 % more area-efficient and 5 % more power-efficient, all while maintaining acceptable error levels. Moreover, in the context of image processing, it demonstrates PSNR and SI values closely aligned with those of standard fixed-point multipliers. In conclusion, our innovative approximate multiplier architecture, grounded in statistical analysis and static compensation, offers substantial improvements in area and power efficiency, rendering it suitable for error-tolerant applications such as digital signal processing and image processing.

Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits using Quantam-Dot Celluar Automata (QCA) Technique

Abstract: In this paper, we propose an approximate multiplier that is Approximate computing (AC) offers benefits by reducing the requirement for accuracy, thereby reducing delay. The majority logic (ML) gate functions as the fundamental logic block of many emerging nanotechnologies. These adders are designed to prevent the propagation of inexact carry-out signals to higher order computing parts to enhance accuracy. We implemented the proposed multiplier by using a unique partial product reduction (PPR) circuitry, which was based on the parallel approximate 6:3 compressor. The implemented by quantum-dot cellular automata (QCA) are analyzed to evaluate the adder designs. A significant improvement is observed over previous designs based on the experimental results. The proposed design is further designed using kogge stone adder. Finally, It has added advantage that reduces logic size and facilitates with less power and delay. Here we are using Verilog HDL and Xilinx ISE14.8 software tools for simulation and synthesis purpose

On the Use of Low-power Devices, Approximate Adders and Near-threshold Operation for Energy-efficient Multipliers

With the rising importance of power consumption in battery-powered devices, approximate computing techniques have emerged as a promising approach to strike a balance between exact computation and power savings, leading to improved delays. This paper investigates the combination of near-threshold operation and approximate adders to design power-efficient multipliers. We analyzed four multiplier architectures using 16 nm low-power and high-performance models. At the transistor level, three strategies for approximate full adders are explored, focusing on both partial product reduction and the final addition stage of the multipliers. Eleven test cases are thoroughly evaluated to identify the most suitable approximate circuit, considering the trade-offs among power, performance, and accuracy. The obtained results demonstrate a substantial reduction in power consumption at near-threshold operation. The replacement of exact full adders with the approximate copy strategy in the least significant bits of the multipliers leads to a reduction of up to 34.4% in power consumption and 19.2% in delay. The design-space exploration carried out in this study provides valuable insights for designers to choose the best approximate multiplier based on specific design requirements.

Improved approximate multiplier architecture for image processing and neural network applications

This paper proposes new approximate unsigned multiplier architecture which aims to reduce the power consumption and area with better accuracy. In our proposed design, the approximation is applied in partial product generation (PPG) and partial product reduction (PPR) stages. In PPG, we proposed two approximate sub-multipliers to reduce the number of partial product rows. For the 8-bit multiplier design, experimental results show an improvement of 38.78% and 50.53% in power and power-delay-product respectively, when the proposed design is compared against the exact design, and 26.11% and 33.17% respectively when compared to existing Ax8-1 design, without compromising on the accuracy. Finally, proposed designs are validated using image processing and neural network applications.

Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction

AbstractThe continued quest for finding a low‐power and high‐performance hardware algorithm for signed number multiplication led to designing a simple and novel radix‐8 signed number multiplier with 3‐bit grouping and partial product reduction performed using magnitudes of the multiplicand and the multiplier. The pre‐computation stage constitutes magnitude calculation and non‐trivial computations required to generate partial products. A new partial product reduction strategy is deployed in the design to improve the speed with low cost. 8×8, 16×16, 32×32, and 64×64 designs are presented for the proposed architectures. Performance results include area, power, delay, and power‐delay‐product of synthesized and post‐layout designs using 32 nm CMOS technology with 1.05 V supply voltage.

High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system

Multiply-Accumulate (MAC) units have been developed recently for various high-performance applications. A crucial component of computing devices, particularly embedded systems, is the MAC unit. The fundamental MAC unit is composed of Multiplier, Adder, and Accumulator. The input for the MAC unit is read from memory cells and given to the MAC multiplier block that multiplies the inputs and passes the result to an adder, which stores the result in memory. One clock cycle is required to complete the full operation. In this manuscript, a lesser power higher speed MAC unit is proposed for Embedding system. High speed binary carry select adders are utilized in MAC units for their speed and integration with three different blocks includes half sum with carry generators (HSCG), final carry generators (FCG), and final sum generators (FSG). For Multiplier design in MAC unit, the counter-based modular Wallace tree multiplier (CMWTM) is utilized, which has power-saving techniques. The proposed CMWTM-HSBCSA-ES MAC unit is implemented in Virtex FPGA development board utilizing Verilog programming language in Xilinx ISE 14.5 design tools. The efficacy of proposed design can be assessed with the metrics such as area, delay, dynamic power consumption, energy, normalized energy and speed. Then the performance of the proposed design provides 16.58%, 41.57% and 25.44% higher speed, 50%, 3.08% and 36% lower delay and 28.03%, 24.50% and 50.32% lower energy compared with the existing MAC unit designs, such as AxMAC-ES, a higher performance MAC unit through incorporating additions with accumulations into partial product reduction procedure (PPR-BA-ES) and high-accuracy MAC technique for unary stochastic computing (TE–SC–ES) respectively.

Efficient Modulo Multiplier

The paper presents the methodology to compute modulo multiplication with the moduli set 2n, 2n−1, 2n+1. In addition to this, designs of the modulo multipliers, namely 2n, 2n−1, and 2n+1 (with n = 4, 8, and 16), have been proposed which are based on half adders, full adders, 4:3 compressor, 7:3 compressor, and the multi-column compressor namely 5,5:4. The gate level design of 4:3 compressor is carried out by solving the truth table using the K-map reduction. To verify the functionalities we have implemented the proposed modulo multipliers using VHDL coding in Xilinx 14.2 design suite. Simulation using Virtex-6 device has been performed to estimate delay, power consumption, and power-delay product (PDP). Moreover, the modulo multipliers are simulated in Cadence RC compiler using 0.18 µm technology to estimate the area. One of the major contributions to the arts of this work is in the partial product reduction stage which utilizes the multi-column 5,5:4 compressor to reduce power and area. The modulo 2n−1 multiplier of operand size 4-bit shows an improvement of 66.34% in terms of area over the best-reported paper. On the other hand, the modulo 2n+1 multiplier of operand size 4-bit shows an improvement of 58.59% terms of in area and the same of operand size 8-bit shows an improvement of 22.72% over the best-reported paper. The proposed algorithms of moduli multiplication are applicable to Booth multiplication of signed numbers.

Design and evaluation of ultra‐fast 8‐bit approximate multipliers using novel multicolumn inexact compressors

SummaryA multiplier, as a key component in many different applications, is a time‐consuming, energy‐intensive computation block. Approximate computing is a practical design paradigm that attempts to improve hardware efficacy while keeping computation quality satisfactory. A novel multicolumn 3,3:2 inexact compressor is presented in this paper. It takes three partial products from two adjacent columns each for rapid partial product reduction. The proposed inexact compressor and its derivatives enable us to design a high‐speed approximate multiplier. Then, another ultra‐fast, high‐efficient approximate multiplier is achieved by utilizing a systematic truncation strategy. The proposed multipliers accumulate partial products in only two stages, one fewer stage than other approximate multipliers in the literature. Implementation results by the Synopsys Design Compiler and 45 nm technology node demonstrate nearly 11.11% higher speed for the second proposed design over the fastest existing approximate multiplier. Furthermore, the new approximate multipliers are applied to the image processing application of image sharpening, and their performance in this application is highly satisfactory. It is shown in this paper that the error pattern of an approximate multiplier, in addition to the mean error distance and error rate, has a direct effect on the outcomes of the image processing application.

Implementation of ALU Using Modified Radix-4 Modified Booth Multiplier

Abstract: In this project, we propose a novel multiplier hardware design based on a radix - 4 modified booth encoder. The standard modified Booth encoding (MBE) provides an uneven partial product array due to the extra partial product bit at the least significant bit position of each partial product row. In this brief, a simple technique for constructing a regular partial product array with fewer partial product rows and low overhead is provided, reducing the complexity of partial product reduction as well as the space, time, and power of MBE multipliers. A SPST-based adder is examined and designed for the reduction of power in partial product reduction

Design and Analysis of High Speed Multiply and Accumulation Unit for Digital Signal Processing Applications

Unit for Digital Signal Processing Applications
 
 Kausar Jahan1, Pala Kalyani2, V Satya Sai3, GRK Prasad4, Syed Inthiyaz5, Sk Hasane Ahammad6
 1Department of ECE, Dadi Institute of Engineering and Technology
 Anakapalle, Andhra Pradesh, India
 2Department of ECE, Vardhaman College of Engineering
 Kacharam, Shamshabad, India
 3Department of ECE, Koneru Lakshmaiah Education Foundation
 Guntur, India-522502
 4Department of ECE, Koneru Lakshmaiah Education Foundation
 Guntur, India-522502
 5Department of ECE, Koneru Lakshmaiah Education Foundation
 Guntur, India-522502
 6Department of ECE, Koneru Lakshmaiah Education Foundation
 Guntur, India-522502
 
 Abstract—The fundamental component used in many of the Digital signal Processing (DSP) applications are Multiply and Accumulation Unit (MAC). In the literature, a multiplier consists of greater number of full adders and half adder in partial product reduction stage, which increases the hardware complexity and critical path delay to MAC unit. To overcome this problem, two novel multipliers are proposed in this article. The proposed multipliers are designed and implemented in hardware, which reduces the circuit complexity and improves the overall performance of the MAC unit with less delay. The proposed multipliers are compared with the 4-bit existing designs and observed that the number of slices Look Up Tables (LUTs) are minimized from 113 to 43, Slices are reduced from 46 to 14, Full Adders (FAs) are lessened from 28 to 23, bonded Input Output Blocks (IOBs) and Half Adders (HAs) were not altered. The time delay is reduced from 14.251ns to 7.876ns. The proposed multipliers are compared in the literature with the 8-bit multiplier, then the number of Slice LUTs are reduced from 510 to 231, Slices are reduced from 218 to 113, FAs are reduced from 120 to 110, HAs are reduced from 56 to 39, time delay is reduced from 26.228ns to12.748ns, but bonded IOBs count remains same. The synthesis and simulations results are verified by using Xilinx ISE 14.7 version tool.

A high‐efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression

SummarySophisticated systems take advantage of approximate circuits for energy management. A gate‐level structure is introduced to make a novel imprecise full adder (FA) cell by the gate diffusion input (GDI) strategy. The carbon nanotube field‐effect transistor (CNTFET) technology lowers the FA power, and the swing issue is resolved by the dynamic threshold (DT) technique. The FA specifications are 10 transistors, two internal nodes, 0.191‐μm2 area, three errors, and an error rate (ER) of 37.5%. Some inputs are directly passed to the final stage of the FA to reduce the delay and dynamic power. The FA is used in three 4:2 compressors with 12, 16, and 20 transistors, respectively. The compressors are based on the modified stacking concept to attain low power, small area, and high speed. The compressors are used up in the partial product reduction tree (PPRT) of a new 8‐bit inexact multiplier. Regarding the multiplier, the power–delay product (PDP) is decreased by 25.21%, and the normalized mean error distance (NMED) shows high accuracy. An imprecise discrete cosine transform (DCT) is implemented by the multiplier for image compression, and compared with the literature, the peak signal‐to‐noise ratio (PSNR) and structural similarity index metric (SSIM) are amended by 8.26% and 7.29%, respectively.

Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits

Approximate computing (AC) offers benefits by reducing the requirement for full accuracy, thereby reducing power consumption and area. The majority logic (ML) gate functions as the fundamental logic block of many emerging nanotechnologies. In this article, ML-based arithmetic circuits, i.e., multibit adders and multipliers, are proposed. These adders are designed to prevent the propagation of inexact carry-out signals to higher order computing parts to enhance accuracy. We implemented the proposed multiplier by using a unique partial product reduction (PPR) circuitry, which was based on the parallel approximate 6:3 compressor. Several logic implementation costs, error metrics, and layouts implemented by quantum-dot cellular automata (QCA) are analyzed to evaluate the adder designs. A significant improvement is observed over previous ML-based designs based on the experimental results. The proposed designs are further evaluated using both a neural network (NN) accelerator and image processing. A structural similarity (SSIM) value of 1 and a peak signal-to-noise ratio (PSNR) value of infinity are achieved by the proposed adder design.

Optimization of Delay IIN Pipeline Mac Unit Using Wallace Tree Multiplier

Abstract: A prompt pipelined MAC unit is implemented in this paper. Due to carrying propagations in additions, including additions of multiplications and additions of accumulations, we will experience a significant path delay as well as a significant increase in power consumption when using the conventional methodology. To resolve these issues, we are including a portion of improvements to the partial product reduction procedure. The pipelined MAC implementation does not complete the addition and accumulation of the most weighted bits until the partial product reduction step of the subsequent multiplication. In order to manage the overspill bits during the partial product reduction procedure, we are designing the small size adder which computes the total number of carries. By comparing with the conventional methodologies, we will get the diminished area as well as power consumption for the proposed pipelined MAC implementation.

Low power, high speed approximate multiplier for error resilient applications

This paper proposes novel constant carry-based approximate compressors for partial product reduction in the binary multiplier. The constant carry compressors have only Sum as output and the output carry bits are either constant 0 or 1 and hence no requirement of logic computation. This will evidently remove the carry chain when these compressors are utilized for column reduction in multipliers. This work examined the 4-bit multiplier with two different constant carry chains (Type-1, Type-2) since there is possibility of two constants. The 8-bit multipliers are built using 4-bit recursively with both the types. By analyzing the two modes, it is concluded that Type-1 i.e., constant carry chain of all zeros is efficient in terms of error and energy. The existing best design of approximate compressor based multipliers (M1, M2) of Ansari et al. (2018) are compared with proposed multipliers. The proposed 8-bit multipliers of either Type-1 or Type-2 work with the maximum delay of 245ps, whereas the existing designs work with maximum delay of 300ps. The proposed designs have constant delay and also nearly 40% energy savings for increase in ER of 2% and the MED increment of 0.72, 3 when compared to M1 and M2 designs respectively. The proposed multiplier effectiveness is demonstrated using image smoothing, edge detection, and Discrete Cosine Transform (DCT), resulting in high acceptable values for quality metrics of Average PSNR, SSIM, and PIQE. The PSNR for DCT is 28 dB with SSIM of 0.99 and PIQE of 42.9.

Optimized Image Multiplication with Approximate Counter Based Compressor

The processor is greatly hampered by the large dataset of picture or multimedia data. The logic of approximation hardware is moving in the direction of multimedia processing with a given amount of acceptable mistake. This study proposes various higher-order approximate counter-based compressor (CBC) using input shuffled 6:3 CBC. In the Wallace multiplier using a CBC is a significant factor in partial product reduction. So the design of 10-4, 11-4, 12-4, 13-4 and 14-4 CBC are proposed in this paper using an input shuffled 6:3 compressor to attain two stage multiplications. The input shuffling aims to reduce the output combination of the 6:3 compressor from 64 to 27. Design of 15-4, 10-4, 9-4, and 7-3 CBCs are performed using the proposed 6:3 compressor and the results obtained are compared with the existing models. These existing models are constructed using multiplexers and 5-3 CBC. When compared to input shuffled 5-3 the proposed 6:3 compressor shows better results in terms of area, power and delay. An approximation is performed on the 6:3 compressor to further reduce the computational energy of the system which is optimal for multimedia applications. The major contribution of this work is the development of two stage multiplier using various proposed CBC. All designs of the approximate compressor (AC) and true compressor (TC) are analysed with 8 x 8 and 16 x 16 image multiplication. The proposed multipliers also provide adequate levels of accuracy, according to the MATLAB simulations, in addition to greater hardware efficiency. As the result approximate circuits over image processing shows the stunning performance in many deep learning network in the current research which is only oriented to multimedia.