High-Level Synthesis (HLS) has evolved significantly due to the increasing complexity of integrated circuit design and the demand for efficient design methodologies. HLS, which raises the abstraction level of design specification, allows designers to focus on hardware functionality, thus enhancing productivity and reducing verification efforts. However, a key challenge in HLS is efficiently exploring the vast design space to find the Pareto-optimal designs. In this paper, we introduce a novel approach for multi-objective design space exploration in HLS. Our methodology decomposes the design space exploration problem into simpler sub-problems using the Multi-Objective Evolutionary Algorithm based on Decomposition (MOEA/D) framework and utilizes the Estimation of Distribution Algorithm (EDA) to build a probabilistic model for generating candidate solutions, thereby reducing the required number of expensive synthesis runs. Experimental results show that the proposed method has a faster convergence speed and reduces the number of syntheses by 24.34% to 32.01%, which significantly outperforms state-of-the-art works. Our approach achieves superior Pareto fronts with the lowest average ADRS value, outperforming Lattice-expl, ϵ -Constraint GA, and NSGA-II by 85.64%, 39.90%, and 33.31% respectively.