Parasitic Circuit Research Articles

Smart Self-Driving Multilevel Gate Driver for Fast Switching and Crosstalk Suppression of SiC MOSFETs

Wide-bandgap devices, such as silicon carbide and gallium nitride, have high switching speed potential. However, the actual speed in practical application is limited by circuit parasitics and interaction between high-side switch and lowside switch in a phase-leg configuration, known as crosstalk effect. This article proposes an isolated voltage source gate driver with crosstalk suppression capability to take full advantage of the inherent high switching speed ability of silicon-carbide devices. By applying variable gate voltage through the auxiliary circuit, the crosstalk problem can be mitigated. Using the original gate-source voltage as auxiliary circuit driving signal, the gate driver does not introduce any extra control signals, which avoids additional signal/power isolations and makes the auxiliary circuit very convenient to be implemented on the existing commercial gate driver. The auxiliary circuit makes the gate voltage rise from 0 V other than -5 V when the switch turns on, leading to faster switching speed and lower switching loss compared with a traditional gate driver. LTSPICE simulation and double pulse test experiment based on 1.2-kV/60-A silicon-carbide MOSFETs are conducted to evaluate the crosstalk suppression capability of the proposed gate driver.

Equivalent Circuit Model of Coaxial Probe-Fed Quasi-Lumped Element Resonator Antenna

Equivalent circuit model of a coaxial probe-fed quasi-lumped element resonator antenna is proposed. The proposed resonator is a periodic interdigital lumped element structure whose resonance does not depend on the electrical length but instead on some intrinsic circuit components, with attendant small size as a premium. The derived equivalent circuit components are extracted using the Agilent Advance Design System (ADS) software. The equivalent circuit model of the coaxial-feed probe is derived based on the simplest uniform-current model of a coaxial probe based on assumption that 1) all the higher-order evanescent have been included analytically in the parasitic circuit elements, and 2) only the propagating modes needs to be considered. The entire structure is further investigated using numerical EM solver such as finite integration technique (FIT) method in order to further compare the level of agreement. The derived equivalent circuit model has been validated by analytical formulae, numerical simulations, and measurement-based method.

A High-Sensitivity AlGaN/GaN HEMT Terahertz Detector With Integrated Broadband Bow-Tie Antenna

Many emerging applications in the terahertz (THz) frequency range demand highly sensitive, broadband detectors for room-temperature operation. Field-effect transistors with integrated antennas for THz detection (TeraFETs) have proven to meet these requirements, at the same time offering great potential for scalability, high-speed operation, and functional integrability. In this contribution, we report on an optimized field-effect transistor with integrated broadband bow-tie antenna for THz detection (bow-tie TeraFET) and compare the detector's performance to other state-of-the-art broadband THz detector technologies. Implemented in a recently developed AlGaN/GaN MMIC process, the presented TeraFET shows a more than twice performance improvement compared to previously fabricated AlGaN/GaN-HEMT-based TeraFETs. The detector design is the result of detailed modeling of the plasma-wave-based detection principle embedded in a full-device detector model to account for power coupling of the THz radiation to the intrinsic gated FET channel. The model considers parasitic circuit elements as well as the high-frequency impedance of the integrated broadband antenna, and also includes optical losses from a silicon substrate lens. Calibrated characterization measurements have been performed at room temperature between 490 and 645 GHz, where we find values of the optical (total beam power referenced) noise-equivalent power of 25 and ${\text{31 pW}}/\surd{\text{Hz}}$ at 504 and 600 GHz, respectively, in good agreement with simulation results. We then show the broadband detection capability of our AlGaN/GaN detectors in the range from 0.2 to 1.2 THz and compare the TeraFETs’ signal-to-noise ratio to that of a Golay cell and a photomixer. Finally, we demonstrate an imaging application in reflection geometry at 504 GHz and determine a dynamic range of >40 dB.

Measurement and Extraction of Parasitic Parameters of Quasi-Vertical Schottky Diodes at Submillimeter Wavelengths

This letter reports on a method for extracting parasitic equivalent-circuit model parameters at submillimeter-wave frequencies. The devices investigated are quasi-vertical gallium arsenide Schottky diodes integrated on silicon. The technique utilizes measurements of coplanar waveguide-fed passive structures in the WR-2.2 band (325–500 GHz), which are fabricated on the same wafer as the diodes. These structures consist of short- and open-circuited terminations that allow direct measurement of the parasitic circuit elements associated with the device. The values of the parasitic elements obtained using this method are in agreement with the values reported in the literature for diodes of comparable geometry.

A Measurement-Based Wide-Frequency Model for Aircraft Wound-Rotor Synchronous Machine

For the safety of the wound-rotor synchronous machine (WRSM) in aircraft applications, the overvoltage at the motor terminals, electromagnetic interference (EMI) performance, and bearing currents as well as the loss analysis are the core areas to be addressed. The high-frequency (HF) modeling method of the WRSM, which has a strong relationship with all these core areas, is a very critical theme. In this paper, a measurement-based wide-frequency (WF) modeling method to characterize the impedance of the WRSM is proposed to build a straightforward correlation between fundamental models and HF parasitic circuit elements. In this paper, the voltage-behind-reactance method is applied to demonstrate the rotor-angle-dependent characters in the low-frequency domain, while the vector fitting method is used to parameterize the HF branch for high-accuracy consideration. By doing this, a WF electrical model with multistage RLC units is formed, which comprehensively considers both the saliency character of the machine and frequency range. The WF model is also compatible with the circuit-based simulation. Finally, the EMI prediction orientated simulation and experimental results are implemented on a 10 kVA WRSM prototype to verify the correctness and advantages of the proposed modeling method.

Application-Oriented Investigation of Parasitic Limitation on Multilevel Modulation of High-Speed VCSELs

In this paper, we present an application-oriented investigation of parasitic limitation on the large signal performance of VCSELs when multilevel modulation is applied. VCSELs with different damping are taken into consideration. The parasitic parameters are extracted by fitting the measured $S_{11}$ data toward a frequency of 40 GHz. In the large signal analysis, four-level pulse amplitude modulation (PAM-4) signaling is embedded into the tool of VCSEL integrated spatio-temporal advanced simulator (VISTAS) and analyzed with extracted parameters. The transmitter and dispersion eye closure quaternary (TDECQ) of the 50-Gb/s PAM-4 signals from VCSEL model is evaluated to understand the relationship between parasitic parameters and signal quality. It is found that the over-damped VCSEL would benefit from larger parasitic bandwidth for PAM-4 modulation while the under-damped VCSEL with moderate parasitic bandwidth would present the best large signal response for PAM-4 modulation. The results indicate that for multilevel modulation, the parasitic parameters need to be carefully designed according to the VCSEL intrinsic parameters to achieve better large signal performance. By co-optimizing the key parasitic parameters, the parasitic circuit design criteria for each type of VCSEL are provided to obtain the best large signal performance under multilevel modulation. The results could provide a designing guidance for VCSELs aiming at multilevel modulation applications.

Imbalance Current Analysis and Its Suppression Methodology for Parallel SiC MOSFETs with Aid of a Differential Mode Choke

Parallel connection of silicon carbide (SiC) MOSFETs is a cost-effective solution for high-capacity power converters. However, transient imbalance current, during turn- on and - off processes, challenges the safety and stability of parallel SiC MOSFETs. In this paper, considering the impact factors of device parameters, circuit parasitics, and junction temperatures, in-depth mathematical models are created to reveal the electrothermal mechanisms of the imbalance current. Moreover, with the incorporation of a differential mode choke (DMC), an effective approach is proposed to suppress the imbalance current among parallel SiC MOSFETs. Physics concepts, operation principles, and design guidelines of the DMC-based suppression method are fully presented. Besides, to reduce the equivalent leakage inductance and equivalent parallel capacitance of the DMC, winding patterns of the DMC are comparatively studied and optimized to suppress turn- off over-voltage and switching ringing. Concerning the influence of winding patterns, load currents, gate resistances, and junction temperatures, experimental results are comprehensively demonstrated to confirm the validity of theoretical models and the function of the proposed DMC-based suppression method. It is turned out the low-cost DMC is easy to design and utilize without complex feedback circuits or control schemes, which is a cost-effective component to guarantee consistent and synchronous on–off trajectories of parallel SiC MOSFETs.

Enhancement of the MQW-RSOA's Small-Signal Modulation Bandwidth by Inductive Peaking

We present a small-signal model of the multiple quantum well (MQW) reflective semiconductor optical amplifier (RSOA) with the accompanying parasitic circuit, followed by a numerical simulation of its modulation response. We analyze the corresponding $-$ 3 dB bandwidth's dependence on the bias current, optical power of the input signal, and the RSOA's active region length. Material, electrical and optical parameters, and the overall design of MQW RSOA are derived bottom-up from the fundamental principles. It is shown that the modulation response, resulting from either intrinsic or parasitic-like model (including transport effects), usually provides high $-3$ dB bandwidth, which is clamped by the chip's parasitics, leading to a relatively poor external modulation bandwidth. This issue can be overcome by an advanced design of the RSOA structure, as the one proposed in this paper and with the optimized bonding, which may improve the external modulation bandwidth significantly through the inductive peaking effect (IPE). Moreover, IPE's efficiency increases if the intrinsic or parasitic-like modulation bandwidth is in the proximity of the parasitic circuit resonant frequency.

Ultra-Compact TSV-Based L-C Low-Pass Filter With Stopband Up to 40 GHz for Microwave Application

In this paper, an ultra-compact low-pass filter (LPF) with wide stopband is proposed based on lumped L-C structure in through-silicon via-based 3-D stacked configuration. The spiral inductor (L), interdigital capacitor (C), and the proposed LPF are theoretically analyzed based on parasitic parameters and equivalent circuit models. To evaluate the characteristics, the proposed LPF is simulated by HFSS, fabricated with CMOS-process-compatible technology, and measured with de-embedding method. Simulation and measured results are in good agreement. Compared with the other literature, the proposed LPF has the most compact size of $0.028\lambda _{g }\times 0.017 \lambda _{g}$ . ( $\lambda _{g}$ is the guide wavelength at $f_{c}$ .) With the cutoff frequency at 10.05 GHz, the filter has an insertion loss of 0.14 dB and reflection loss over 13 dB from dc to 9 GHz in the passband. The suppression levels are better than 20 dB from 20.4 up to 40 GHz in the stopband.

Topology optimization of conductors in electrical circuit

This study proposes a topology optimization method for realizing a free-form design of conductors in electrical circuits. Conductors in a circuit must connect components, such as voltage sources, resistors, capacitors, and inductors, according to the given circuit diagram. The shape of conductors has a strong effect on the high-frequency performance of a circuit due to parasitic circuit elements such as parasitic inductance and capacitance. In this study, we apply topology optimization to the design of such conductors to minimize parasitic effects with maximum flexibility of shape manipulation. However, when the distribution of conductors is repeatedly updated in topology optimization, disconnections and connections of conductors that cause open and short circuits, respectively, may occur. To prevent this, a method that uses fictitious electric current and electric field calculations is proposed. Disallowed disconnections are prevented by limiting the maximum value of the fictitious current density in conductors where a current is induced. This concept is based on the fact that an electric current becomes concentrated in a thin conductor before disconnection occurs. Disallowed connections are prevented by limiting the maximum value of the fictitious electric field strength around conductors where a voltage is applied. This is based on the fact that the electric field in a parallel plate capacitor is inversely proportional to the distance between the plates. These limitations are aggregated as a single constraint using the Kreisselmeier-Steinhauser function in the formulation of optimization problems. This constraint prevents only disallowed disconnections and connections, but does not prevent allowed topology changes. The effectiveness of the constraint is confirmed using simple examples, and an actual design problem involving conductors in electromagnetic interference filters is used to verify that the proposed constraint can be utilized for conductor optimization.

Prevention of Oscillatory False Triggering of GaN-FETs by Balancing Gate-Drain Capacitance and Common-Source Inductance

Gallium-nitride-field-effect transistors (GaN-FETs) are promising switching devices with fast switching capability. However, they commonly have low gate threshold voltage, suffering from susceptibility to the false triggering. Particularly, the oscillatory false triggering, i.e., a self-sustaining repetitive false triggering, can occur after a fast switching, which is a severe obstacle for industrial applications. The purpose of this paper is to elucidate the design instruction for preventing this phenomenon. The oscillatory false triggering is known to be caused by the parasitic oscillator circuit formed of a GaN-FET, its parasitic capacitance and the parasitic inductance of the wiring. This paper analyzed the nonoscillatory condition of this oscillator. The result revealed an appropriate ratio between the gate-drain capacitance and the common-source inductance is a key to prevent the oscillatory false triggering. Experiment successfully verified this analysis result, supporting the effectiveness of the appropriate design of this ratio for preventing the oscillatory false triggering.

Improved Performance of CMOS Terahertz Detectors by Reducing MOSFET Parasitic Capacitance

The parasitic circuit elements significantly affect rectification performance of metal-oxide-semiconductor field-effect transistor devices. In this paper, we develop a gate-source parasitic capacitance reduction technique by shifting the source lightly doped drain region and analyze the effectiveness on the improved performance of complementary metal-oxide-semiconductor (CMOS) terahertz (THz) detectors. It is experimentally found that for a 0.65-THz integrated CMOS detector, the maximum improvement of voltage responsivity and noise-equivalent power can be 155% and 70%, respectively, by suppressing the gate-source parasitic capacitance. The device simulation further quantitatively evaluates the gate-source parasitic capacitance under different gate-source overlap areas in the novel fabricated transistor structure. It reveals that a smaller gate-source overlap area can result in a lower gate-source parasitic capacitance, which is more favorable for reducing input THz signal leakage and therefore for increasing the THz responsivity. The works open a wide range of possibilities for the ease of design and fabrication of the high-performance THz detectors in standard CMOS technology.

Design and Analysis of a Programmable Receiver Front End With Time-Interleaved Baseband Analog-FIR Filtering

This paper presents time interleaving as an approach to improve the performance of programmable receiver front ends based on filtering-by-aliasing. Using two parallel periodically time-varying paths, a sharp programmable filtering response is produced at RF, while achieving a good wideband S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> . The implemented receiver achieved a filter stopband suppression of 70 dB with a transition band of only 4× RF bandwidth, while S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> is better than -10 dB throughout most of the receiver local oscillator range. Analysis for achieved S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> and noise figure are shown, while detailing methods to improve filtering performance in the presence of important circuit parasitics. The effects of mismatches between time-interleaved paths are also analyzed and quantified.

Novel Common-Mode Current Suppression Method in Transformerless PV Grid-Connected System

The existence of high-frequency components in common-mode (CM) current would reduce the stability of a non-isolated PV grid-connected system. It has great impacts on the output power quality when the generated power from PV is low. The method of single CM inner loop in suppressing the high-frequency components has poor effect. Based on the CM equivalent circuit model and the cause analysis of the CM current, a novel dual CM inner loops method is proposed to restrain the high-frequency components in CM current. This method not only meets the grid connection demand of CM current, but also overcomes the high frequency resonant problem. Furthermore, the high-frequency components in CM current from the outer parasitic circuit are substantially reduced. Finally, the proposed method is verified by simulation and experimental results.

Modeling and Analysis of Large-Signal RFI Effects in MOS Transistors

The ability of radio-frequency (RF) interference signals to upset or disrupt electronic equipment is a matter of concern, and identification of the physical mechanisms leading to device malfunction is of prime importance. This paper presents experimental and theoretical results and analyzes the effects of a large-signal microwave excitation up to 2 GHz on several commercial small-signal MOS transistors. For frequencies beyond the maximum operating frequency, experimental results show RF signal rectification in the devices, and these results are confirmed by SPICE simulations using extracted models for the transistors, including package and test circuit parasitics, with excellent agreement with experiments. Analysis of internal transistors currents and voltages finally leads to the conclusion that the observed rectification effect is not due to active nonlinearities of the devices, but rather due to the nonlinear overlap and parasitic drain–bulk diode capacitances of the MOS transistors. In particular, the role of the nonlinear voltage dependence of the junction capacitance is highlighted. Finally, a simplified model is proposed to reproduce this behavior.

Theoretical Analysis of Circuit Non-Idealities in a Passive Spectrum Scanner Based on Periodically Time-Varying Circuit Components

Spectrum scanners based on passive, linear periodically time-varying $RC$ circuits have been shown to be highly linear and consume low power. They rely on the Filtering by Aliasing technique to achieve sharp filtering from a continuous-time input to a discrete-time output. The presence of circuit parasitics can adversely affect scanner performance. Hence, this paper presents a theoretical analysis of the main circuit non-idealities affecting them. In addition, circuit and signal processing techniques to mitigate the effect of these non-idealities is presented and verified through both simulation and chip measurement results.

Source engineering on ruggedness and RF performance of n-channel RFLDMOS

The state-of-art n-channel RFLDMOS (Radio Frequency Lateral Double-diffusion Metal Oxide Semiconductor) FETs with different source engineering have been fabricated using 0.18 μm BCD (Bipolar/COMS/DMOS) process. The ruggedness and RF performance of RFLDMOS have been studied with TLP (Transmission Line Pulse) test, VSWR (Voltage Stop Wave Ratio) test, and source/load-pull test. It was found that PBL (P+ buried layer) source engineering could improve its ruggedness remarkably. The mechanism of this improvement has been studied by introducing equivalent parasitic circuit. The dominant factor is the resistor RB which delays turn-on characteristic of parasitic NPN in equivalent circuit. And the computational model of RB is proposed. Furthermore, the optimal performance of RFLDMOS has also been discussed.

A Metabolite-Triggered Tuft Cell-ILC2 Circuit Drives Small Intestinal Remodeling

The small intestinal tuft cell-ILC2 circuit mediates epithelial responses to intestinal helminths and protists by tuft cell chemosensory-like sensing and IL-25-mediated activation of lamina propria ILC2s. Small intestine ILC2s constitutively express the IL-25 receptor, which is negatively regulated by A20 (Tnfaip3). A20 deficiency in ILC2s spontaneously triggers the circuit and, unexpectedly, promotes adaptive small-intestinal lengthening and remodeling. Circuit activation occurs upon weaning and is enabled by dietary polysaccharides that render mice permissive for Tritrichomonas colonization, resulting in luminal accumulation of acetate and succinate, metabolites of the protist hydrogenosome. Tuft cells express GPR91, the succinate receptor, and dietary succinate, but not acetate, activates ILC2s via a tuft-, TRPM5-, and IL-25-dependent pathway. Also induced by parasitic helminths, circuit activation and small intestinal remodeling impairs infestation by new helminths, consistent with the phenomenon of concomitant immunity. We describe a metabolic sensing circuit that may have evolved to facilitate mutualistic responses to luminal pathosymbionts.

A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions

An integer linear programming-based framework to identify the current-mode threshold logic functions is presented. The approach minimizes the transistor count and benefits from a generalized definition of threshold logic functions. It is shown that the threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. A novel implementation of rational weights is proposed. Process variations, transistor aging, and circuit parasitics are taken into consideration. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of the existing threshold functions is reduced when comparing with the traditional CMOS-based threshold logic implementation.

Sub-millimeter-Wave Equivalent Circuit Model for External Parasitics in Double-Finger HEMT Topologies

We present a novel distributed equivalent circuit that incorporates a three-way-coupled transmission line to accurately capture the external parasitics of double-finger high electron mobility transistor (HEMT) topologies up to 750 GHz. A six-step systematic parameter extraction procedure is used to determine the equivalent circuit elements for a representative device layout. The accuracy of the proposed approach is validated in the 90–750 GHz band through comparisons between measured data (via non-contact probing) and full-wave simulations, as well as the equivalent circuit response. Subsequently, a semi-distributed active device model is incorporated into the proposed parasitic circuit to demonstrate that the three-way-coupled transmission line model effectively predicts the adverse effect of parasitic components on the sub-mmW performance in an amplifier setting.