Abstract
Spectrum scanners based on passive, linear periodically time-varying $RC$ circuits have been shown to be highly linear and consume low power. They rely on the Filtering by Aliasing technique to achieve sharp filtering from a continuous-time input to a discrete-time output. The presence of circuit parasitics can adversely affect scanner performance. Hence, this paper presents a theoretical analysis of the main circuit non-idealities affecting them. In addition, circuit and signal processing techniques to mitigate the effect of these non-idealities is presented and verified through both simulation and chip measurement results.
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