Parasitic Capacitance Components Research Articles

Parasitic Capacitance Model for Stacked Gate-All-Around Nanosheet FETs

Gate-all-around (GAA) nanosheet field-effect transistors (NSFETs) are hailed as the most promising architecture for the incessant scaling of MOSFETs to the sub-5-nm technology node and beyond. Although the GAA structure and the ultra-thin channel lead to a significantly improved static performance owing to the enhanced electrostatic integrity and higher immunity against the short-channel effects, the vertical stacking and the inherent 3-D-geometry result in a large parasitic capacitance and may degrade the dynamic performance. Therefore, it becomes imperative to analyze the parasitic capacitance components in GAA NSFETs and provide design guidelines for optimizing the dynamic performance. To this end, in this work, we have formulated an analytical model for the total gate parasitic capacitance in GAA NSFETs, considering contributions from different parasitic capacitance components. Furthermore, we have also investigated the variation in parasitic capacitance components with the structural parameters for design optimization of GAA NSFETs from a dynamic performance perspective. The result of the developed model is in good agreement with TCAD simulation result indicating the efficacy of the analytical model.

Impact of Parasitic Gate Capacitance on RF Performance in GaN-Based HEMTs for X-Band Applications

GaN-based high-electron-mobility transistors (HEMTs) are intensively researched for high-power radio frequency (RF), low noise, and aerospace applications, thanks to their high breakdown electric field, high carrier mobility and density at the hetero-interface, and wide bandgap [1-2]. For the improvement of RF performance, various approaches have been reported, including T-gate structure [3-4], surface passivation [5], n+-regrown source and drain contact [6], thin barrier structure [7], and graded-channel [8]. Among them, the T-gate structure has been extensively employed for the reduction of the gate resistance (Rg ) and thereby improvement of the RF performance. However, the usage of the wide T-gate structure enlarges parasitic gate capacitance components, which deteriorates the RF performance. As a result, one should pay careful attention to the dimension of the wide T-gate structure to reduce Rg as much as possible, not to enlarge the parasitic gate capacitance components. This motivates us to explore the optimum dimension of the wide T-gate structure in GaN-based HEMTs for X-band RF applications.To investigate the detailed impact of the gate resistance and parasitic gate capacitance components, we fabricated LG = 0.15 μm GaN-based HEMTs with various dimensions of the T-gate head from 0.5 to 0.8 μm during an e-beam lithography process step. The unit gate width (WG ) and number of gate finger (NF ) were 100 μm and 2, respectively.For comparison of the device characteristics with respect to the dimension of the gate head, DC and RF measurements were conducted for the fabricated GaN-based HEMTs with various dimensions of T-gate head. The DC characteristics in terms of the threshold voltage (VTH ), the maximum transconductance (gm,max ), and the saturation drain current (Id,sat ) were almost identical, regardless of the dimension of the T-gate head. On the contrary, the current-gain cut-off frequency (fT ) and maximum oscillation frequency (fMAX ) were improved by 26.5% and 21.0%, respectively, when the T-gate head size was reduced from 0.8 to 0.5 μm.In an effort of explore the origin of the dependence of the T-gate head on the RF performance, we have carried out small-signal modeling to extract the parasitic gate capacitance and gate resistance components from the measured RF data. As the T-gate head size was reduced from 0.8 to 0.5 μm, the gate-source parasitic capacitance component (Cgs_par ) was reduced by 19%, while the gate resistance component was increased by 32%. In our device design and fabrication, it turned out that the reduction of Cgs_par was more beneficial than the increase of Rg , leading to the improved RF performance with the gate head size decrease.In this work, our systematic research revealed that, unlike earlier reports [3-4], the reduction of the parasitic gate capacitance was essential for the improvement of the RF performance as opposed to the reduction of the gate resistance in LG = 0.15 μm GaN-based HEMTs for X-band RF applications. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MIST) (No. NRF-2021M3C1C3097672).

Impact of the Source-to-Drain Spacing on the DC and RF Characteristics of InGaAs/InAlAs High-Electron Mobility Transistors

In this letter, we investigated the impact of the source-to-drain spacing ( ${L}_{\textsf {SD}}$ ) on the dc and high-frequency characteristics of indium-rich In0.8Ga0.2As/In0.52Al0.48As high-electron mobility transistors (HEMTs) on a 3-in InP substrate. ${L}_{g} = \textsf {87}$ nm HEMTs with different values of ${L}_{\textsf {SD}}$ were fabricated ranging from 1.55 to $0.8~\mu \text{m}$ , and their dc and RF responses were measured and analyzed in detail. In order to suppress the increase of the parasitic gate capacitance, we maintained the gate stem height as high as 200 nm in our device fabrication. Both the maximum transconductance (gm_max) and on-resistance ( ${R}_{\textsf {ON}}$ ) improved as ${L}_{\textsf {SD}}$ scaled down to $0.8~\mu \text{m}$ . At the same time, the high-frequency figures of the merit, such as current-gain cutoff frequency ( ${f}_{T}$ ) and maximum oscillation frequency ( ${f}_{\textsf {max}}$ ), increased with the reduction of ${L}_{\textsf {SD}}$ . These improvements are attributed to the reduction of series resistances. In particular, the ${L}_{g} =87$ nm device with an ${L}_{\textsf {SD}} = \textsf {0.8} \mu \text{m}$ exhibited an excellent combination of dc and RF characteristics, such as gm_max = 2.7 mS/ $\mu \text{m}$ , ${R}_{\textsf {ON}} = \textsf {318}\,\,\Omega \cdot \mu \text{m}$ , ${f}_{T} = \textsf {519}$ GHz, and ${f}_{\textsf {max}} = \textsf {645}$ GHz, respectively. The results obtained in this letter indicate that the reduction of ${L}_{\textsf {SD}}$ down to $0.8~\mu \text{m}$ continues to improve both the dc and RF characteristics of the InGaAs/InAlAs HEMTs, and a possible increase in parasitic capacitance components, associated with a T-shaped, is still negligible in our device architecture.

All Regimes Parasitic Capacitances Extraction Using a Multi-Channel CBCM Technique

In this paper, we propose a multi-channel charge-based capacitance measurement (MCCBCM) technique for parasitic capacitances extraction of MOSFETs. The proposed technique is developed from a leakage- and parasitic-insensitive charge-based capacitance measurement technique, which is applied to measure gate-to-channel capacitance in certain regimes. Using the MCCBCM technique, we can measure all of the parasitic capacitance components of an MOSFET which are related to its terminals, such as the gate-to drain capacitance ( $ {C_{GD}}$ ), gate-to-source capacitance ( $ {C_{GS}}$ ), gate-to-bulk capacitance ( $ {C_{GB}}$ ), and so on. We designed a complex control methodology for the MCCBCM circuit. Specific control methods are provided for different parasitic capacitance components when MOSFETs work in different regimes. We can measure capacitances of sub-femto-farad level in all regimes, including the accumulation, depletion, and inversion regimes.

Investigation of RC parasitics considering middle-of-the-line in si-bulk FinFETs for Sub-14-nm node logic applications

In this brief, we systematically investigated the effects of fin pitch (FP) and fin height ( $H_{\textrm {fin}}$ ) on parasitic resistances and capacitances to achieve the best $RC$ delay, which is an adequate metric of the ac behavior of FinFETs, for Si bulk n/pFinFETs in system-on-a-chip applications. The $RC$ delays were directly extracted from the fully calibrated technology computer aided design $I$ – $V/C$ – $V$ simulation results and quantitatively analyzed using parasitic capacitance components, including a middle-of-the line configuration up to Metal 1. When FP increased, the $RC$ delay likewise increased due to greater $C_{\textrm {gg}}$ . On the other hand, the $RC$ delay mostly decreased due to greater ON-current as the $H_{\textrm {fin}}$ increased. The $RC$ delay with different power supply voltages ( $V_{\textrm {DD}} = 0.55$ and 0.75 V) was also studied to see the effect of $V_{\textrm {DD}}$ scaling. Finally, a selective deposition was suggested to improve the $RC$ delay about 13%.

Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance

Parasitic capacitances have become a main issue for advanced technology nodes. In this paper, we develop analytical models for parasitic capacitance components for several device structures, including bulk devices, fully depleted silicon-on-insulator devices, and double-gate devices. With these models, we analyze the impact of parasitic capacitances on the circuit-level performance for logic applications. Si complementary metal-oxide-semiconductor roadmap projection is revisited beyond 32-nm technology, with different device design scenarios examined.

Characteristics and circuit model of a field emission triode

A circuit model for a field emission triode has been proposed. The model parameters have been extracted from the fabricated silicon tip array and verified by being compared to the results simulated by circuit simulator (SPICE). The cutoff frequency can be calculated from the parametric capacitance and the transconductance values extracted from measurements. For the field emission triode, the capacitance of 3.45 fF/tip and the transconductance of 0.94 nS/tip have been measured under the emission current of 4.1 nA/tip. From these values, the cutoff frequency is predicted to be 43 kHz but the measured one came out to be 6 kHz because of the parasitic capacitance components.

DC–coupled broadband and gain controllable monolithic amplifier circuits

AbstractThis paper will describe a method for broadening the bandwidth of gain controllable monolithic amplifier circuits for the purpose of the application to the repeater circuits in the Gb/s optical transmission systems. The gain controllable differential amplifier circuit exhibits narrower bandwidth because of larger parasitic capacitance components in comparison with basic differential amplifier circuits due to the complicated circuit configuration to control the gain. Also, when the peaking method for broadening the bandwidth is applied, the peaking amounts exceed the optimum value and becomes unstable in the low‐gain operation even if the peaking amounts are optimized for the high‐gain operations. In this paper, a new gain controllable amplifier circuit using the bias current dependency of differential resistance of diodes is proposed. Furthermore, the circuit is fabricated by using the Si Bipolar Super Self‐Aligned process Technology (SST). A broadband characteristic of 1.6 GHz bandwidth and 29‐dB gain controllable width has been obtained. These are sufficient for the application to the Gb/s optical repeater circuits.