Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance

Abstract

Parasitic capacitances have become a main issue for advanced technology nodes. In this paper, we develop analytical models for parasitic capacitance components for several device structures, including bulk devices, fully depleted silicon-on-insulator devices, and double-gate devices. With these models, we analyze the impact of parasitic capacitances on the circuit-level performance for logic applications. Si complementary metal-oxide-semiconductor roadmap projection is revisited beyond 32-nm technology, with different device design scenarios examined.