Parasitic Bipolar Transistor Action Research Articles

A thorough investigation of hot-carrier-induced gate oxide breakdown in partially depleted N- and P-channel SIMOX MOSFETs

In this paper, the hot-carrier-injected oxide region in the front interfaces is systematically investigated for partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) devices fabricated on a SIMOX wafer. The gate oxide properties associated with channel hot-carrier effects are investigated and the hot-carrier-induced device degradations are analyzed using stress experiments with three main types of hot-carrier injections-maximum gate current, maximum substrate current and parasitic bipolar transistor action. Based on experimental results, the influence of these injected carriers on the gate oxide properties is clarified. As a matter of fact, NMOSFETs degradation mechanism is shown to be caused by hot holes injected into the drain side of the gate oxide, and electrons trapped in the gate oxide can accelerate the gate oxide breakdown. PMOSFETs degradation mechanism depends on the biasing conditions. For the first time, we conclude that the electrical characteristics of NMOSFETs are significantly different from that of PMOSFETs after the gate oxide breakdown. An extensive discussion of the experimental results is provided.

Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-Micron SOI MOSFETs.

AbstractA study of parasitic bipolar junction transistor effects in single pocket thin film siliconon-insulators (SOI) nMOSFETs has been carried out. Characterization and simulation results show that parasitic bipolar junction transistor action is reduced in single pocket SOI MOSFETs in comparison to homogeneously doped conventional SOI MOSFETs. A novel Gate-Induced-Drain-Leakage (GIDL) current technique was used to characterize the SOI MOSFETs. 2 - D simulations were carried out to analyze the reduced parasitic bipolar junction effect in single pocket thin film SOI MOSFETs.

A study on hot-carrier-induced gate oxide breakdown in partially depleted SIMOX MOSFET’s

The hot-carrier-induced oxide regions in the front and back interfaces are systematically studied for partially depleted SOI MOSFET’s. The gate oxide properties are investigated for channel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stress experiments with three typical hot-carrier injection, i.e., the maximum gate current, maximum substrate current and parasitic bipolar transistor action. Experiments show that PMOSFET’s degradation is caused by hot carriers injected into the drain side of the gate oxide and the types of trapped hot carrier depend on the bias conditions, and NMOSFET’s degradation is caused by hot holes. This paper reports for the first time that the electric characteristics of NMOSFET’s and PMOSFET’s are significantly different after the gate oxide breakdown, and an extensive discussion of the experimental findings is provided.

Hot carrier induced degradation in mesa-isolated n-channel SOI MOSFETs operating in a Bi-MOS mode

A thorough investigation of hot carrier effects is made in mesa-isolated SOI nMOSFETs operating in the Bi-MOS mode (abbreviated as Bi-nMOSFETs). As a result of its unique hybrid operation mechanism, significant reduction of hot carrier induced maximum transconductance degradation and threshold voltage shift in the Bi-nMOSFET is observed in comparison with that in the conventional SOI nMOSFETs. Device lifetime of SOI Bi-nMOSFETs and conventional SOI nMOSFETs was roughly estimated for comparison. In view of the analysis of the degradation mechanism, the devices were stressed under different conditions. The post-stress body current and stress body current in Bi-nMOSFETs as a function of the stress time and stress drain voltage were evaluated as further proofs of the aging reasons. The hot electron injection is found to be the dominant degradation process in the SOI Bi-nMOSFETs. Compared with SOI nMOSFETs, SOI Bi-nMOSFETs show better immunity to the parasitic bipolar transistor action due to the body contact. In addition, the positive body bias can result in lowered hot hole injection into the gate oxide due to the provision of the generated hole leakage path, and thus decreased interface traps.

Study of the extended p/sup +/ dual source structure for eliminating bipolar induced breakdown in submicron SOI MOSFET's

Simulation results on a novel extended p/sup +/ dual source SOI MOSFET are reported. It is shown that the presence of the extended p/sup +/ region on the source side, which can he fabricated using post-low-energy implanting selective epitaxy (PLISE), significantly suppresses the parasitic bipolar transistor action resulting in a large improvement in the breakdown voltage. Our results show that when the length of the extended p/sup +/ region is half the channel length, the improvement in breakdown voltage is about 120% when compared to the conventional SOI MOSFET's.

Numerical Analysis of the Electrical Characteristics of Gate Overlapped Lightly Doped Drain Polysilicon Thin Film Transistors

Polycrystalline silicon (polysilicon) thin film transistor (TFT) technology is emerging as a key technology for active matix liquid crystal displays, allowing the integration of both active matrix and driving circuitry on the same substrate. However, conventional self-aligned polysilicon TFTs present several undesired effects in the electrical characteristics, including large off-currents, kink effect and hot carrier instabilities. These effects are related to the presence of high electric fields at the drain junction and drain field relief is essential. Among the different structures proposed to reduce the drain field, the gate overlapped lightly doped drain (GOLDD) structure appears to have a number of advantages. In this work we investigate the electrical characteristics of GOLDD polysilicon TFTs by using 2-dimensional (2D) numerical analysis. From a close analysis of the output characteristics, we have distinguished two saturation regimes: the first related to the conventional formation of the pinch-off region near the LDD, the second one, occurring at higher source-drain voltages, related to the depletion of the LDD region. Impact ionization effects have been also analysed and kink effect in GOLDD structure has been found to be associated with the parasitic bipolar transistor action, similarly to silicon-on-insulator (SOI) devices. At very high source-drain voltages, avalanche breakdown occurs, due to impact ionization occurring at both channel/LD-region and LD-region/n+ region junctions.

Hot-carrier effects and lifetime prediction in off-state operation of deep submicron SOI N-MOSFETs

Hot-carrier effects (HCE) induced by the parasitic bipolar transistor (PBT) action are thoroughly investigated in deep submicron N-channel SOI MOSFETs for a wide range of temperature and gate length. A multistage device degradation is highlighted for all the experimental conditions. Original V/sub t/ variations are also obtained for short-channel devices, a reduction of the threshold voltage being observed for intermediate values of stress time in the case of high stress drain biases. At low temperature (LT), an improvement of the device aging can be obtained in the low V/sub d/ range because of the significant reduction of the leakage current in the PBT regime. However, in the case of high V/sub d/, since the strong leakage current cannot be suppressed at LT, the device aging is larger than that obtained at room temperature. On the other hand, the device lifetime in off-state operation is carefully predicted as a function of gate length with various methods. Numerical simulations are also used in order to propose optimized silicon-on-insulator (SOI) architectures for alleviating the PBT action and improving the device performance and reliability.

Hot-carrier effects and reliable lifetime prediction in deep submicron N- and P-channel SOI MOSFETs

Hot-carrier effects are thoroughly investigated in deep submicron N- and P-channel SOI MOSFETs, for gate lengths ranging from 0.4 /spl mu/m down to 0.1 /spl mu/m. The hot-carrier-induced device degradations are analyzed using systematic stress experiments with three main types of hot-carrier injections-maximum gate current (V/sub g//spl ap/V/sub d/), maximum substrate current (V/sub g//spl ap/V/sub d//2) and parasitic bipolar transistor (PBT) action (V/sub g//spl ap/0). A two-stage hot-carrier degradation is clearly observed for all the biasing conditions, for both N- and P-channel devices and for all the gate lengths. A quasi-identical threshold value between the power time dependence and the logarithmic time dependence is also highlighted for all the stress drain biases for a given channel length. These new findings allow us to propose a reliable method for lifetime prediction using accurate time dependence of degradation in a wide gate length range.

MAXIMUM OPERATING VOLTAGE LIMITATIONS DUE TO PARASITIC BIPOLAR ACTION IN VLSI CMOS

The influence of the PBTA (Parasitic Bipolar Transistor Action) induced by impact ionization on the maximum operating voltages as well as on the isolation performance in VLSI CMOS structures was investigated using the sensitivity of the nMOS- and bipolar-parameters to the operating voltages. Strong coupling between the MOS-and bipolar-currents exists due to the potential drop caused by the impact ionization currents of the nMOSFET. The base currents of the bipolar transistors reduce the measurable substrate current. The maximum operating voltage in CMOS is limited by the impact ionization induced PBTA. The isolation performance is reduced by the collector current of the vertical transistor.

Computer simulation of ionizing radiation burnout in power MOSFETs

The first computer simulation of the ionizing-radiation-induced burnout in power MOSFETs is reported. The modeling results support a current-induced avalanche burnout mechanism at the interface of the epitaxial layer and the substrate coupled with parasitic bipolar transistor action, leading to secondary breakdown and thermal runaway. The simulations allow an evaluation of the effects of semiconductor parameters, device geometry, doping profiles, and bias voltage on the burnout dose-rate threshold. The model provides a method for optimizing the radiation hardness of power MOSFETs. >

Some CMOS device constraints at low temperatures

Two of the CMOS device constraints at low temperatures have been identified, namely, the transconductance and the breakdown voltage roll-off. In the short channel devices, the transconductance first increases then decreases with the decreasing temperature. This transconductance roll-off phenomenon is likely caused by the parasitic series resistance in the source and drain regions. The breakdown voltage of the MOSFET's due to the parasitic bipolar transistor action decreases with the decreasing temperature, which is caused by the increase of the impact ionization rate at low temperatures.