Parametric Yield Loss Research Articles

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond

In an increasing interconnect resistance era and aggressive metal pitch scaling, the elevating RC delay could significantly shadow the improvements from advanced device architectures and become a severe design issue. This paper will holistically analyze the interplay between transistors and interconnect delay and the variability induced by back-end-ofline (BEOL) process for the 5-nm node. A global sensitivity analysis using Monte Carlo simulation is employed as a powerful tool for understanding the significance of different variation sources and propagating these process uncertainties to circuit performance and parametric yield. For the BEOL integration process, our results show that dielectric κ-value is the most sensitive parameter. Regarding the patterning options, the BEOL process using self-aligned quadruple pattering with positive tone process requires more than a 4× process margin and suffers from 50% parametric yield loss. The required guardband for lithoetch litho-etch becomes as critical as for the self-aligned double patterning process when the overlay control is 6× higher than the critical dimension control. For trench patterning using spacerdefined techniques, a negative tone process is required to achieve a large process window. From a design perspective, the wire length in SoC can be optimized using a disruptive architecture as a vertical FET, which could potentially reduce the average wire length by 11%.

Structure-Preserving-Based Model-Order Reduction of Parameterized Interconnect Systems

In recent years, the continued miniaturization of VLSI circuits leads to the need for more efficient simulation of large-scale linear dynamical systems with ever-increasing state-space dimension. The linear dynamical systems in VLSI circuit simulation are RC or RCL models of the VLSI circuit’s interconnected system. Model-order reduction is an important technique to reduce such a high complexity. Along the technology scaling, the indetermination in the manufacturing process causes variations in the critical dimensions and interlevel dielectric thickness of interconnects, which could make the system performance unpredictable and produce a significant parametric yield loss. An efficient exploitation of these design activities results in a parameterized model-order reduction technique able to reduce large systems of equations with respect to all of the variable parameters of the circuit, (i.e., resistance, capacitance, and inductance). For this purpose, we propose a novel parameterized model-order reduction method for interconnect variation systems, which is based on an efficient and reliable combination of invariable structure-preserving model-order reduction (SPMOR) methods and variable parameter retaining schemes. It is referred to as a parameterized interconnect model-order reduction via structure-preserving algorithm. The SPMOR model yields the same form of the original state equation and preserves the passivity of the parameterized RC and RLC networks, like the well-known passive reduced-order interconnect algorithm for nonparameterized RC and RLC networks. The most important benefit it entails is the ability to preserve the probability characteristic of the original interconnect systems. Pertinent numerical examples are proposed to validate the proposed SPMOR approach.

An efficient prediction framework for multi-parametric yield analysis under parameter variations

Due to continuous process scaling, process, voltage, and temperature (PVT) parameter variations have become one of the most problematic issues in circuit design. The resulting correlations among performance metrics lead to a significant parametric yield loss. Previous algorithms on parametric yield prediction are limited to predicting a single-parametric yield or performing balanced optimization for several single-parametric yields. Consequently, these methods fail to predict the multi-parametric yield that optimizes multiple performance metrics simultaneously, which may result in significant accuracy loss. In this paper we suggest an efficient multi-parametric yield prediction framework, in which multiple performance metrics are considered as simultaneous constraint conditions for parametric yield prediction, to maintain the correlations among metrics. First, the framework models the performance metrics in terms of PVT parameter variations by using the adaptive elastic net (AEN) method. Then the parametric yield for a single performance metric can be predicted through the computation of the cumulative distribution function (CDF) based on the multiplication theorem and the Markov chain Monte Carlo (MCMC) method. Finally, a copula-based parametric yield prediction procedure has been developed to solve the multi-parametric yield prediction problem, and to generate an accurate yield estimate. Experimental results demonstrate that the proposed multi-parametric yield prediction framework is able to provide the designer with either an accurate value for parametric yield under specific performance limits, or a multi-parametric yield surface under all ranges of performance limits.

Genetic Algorithm-Based Multi-Objective Optimization for Statistical Yield Analysis Under Parameter Variations

Due to process scaling, variability in process, voltage, and temperature (PVT) parameters leads to a significant parametric yield loss, and thus impacts the optimization for circuit designs seriously. Previous parametric yield optimization algorithms are limited to optimizing either power yield or timing yield separately, without combining them together for simultaneous optimization. However, neglecting the negative correlation between the performance metrics, such as power and timing measurements, will bring on significant accuracy loss. This paper suggests an efficient multi-objective optimization framework based on Bayes’ theorem, Markov chain method, and an NSGA-II-based genetic algorithm. In the proposed framework, power and timing yields are considered as the optimization objectives to be optimized simultaneously, in order to maintain the negative correlation between power and timing metrics. First, the framework explicitly expresses both leakage current and gate delay in terms of the underlying PVT parameter variations. Then, parametric yields for both metrics are predicted by the computation of cumulative distribution function (CDF) based on Bayes’ theorem and Markov chain method. Finally, a NSGA-II-based genetic algorithm is suggested to solve power–timing optimization problem and generate well-distributed Pareto solutions. Experimental results demonstrate that the proposed multi-objective optimization procedure is able to provide the designer with guaranteed trade-off information between power and timing yields and give them the flexibility in choosing the most appropriate solution(s).

Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices

In this paper, we propose to study the impact of 28nm FDSOI technology on energy study. In fact, due to the effects of the Moore’s law, the process variations in current technologies are increasing and have a major impact on power and performance which results in parametric yield loss. Due to this, process variability and the difficulty of modeling accurately transistor behavior impede the dimensions scaling benefits. The Fully Depleted Silicon-On-Insulator (FDSOI) technology is one of the main contenders for deep submicron devices as they can operate at low voltage with superior energy efficiency compared with bulk CMOS. In this paper, we study the static energy on 28nm FDSOI devices to implement sub-threshold circuits. Study of delay vs. static power trade-off reveals the FDSOI robustness with respect to process variations.

Healing of DSP Circuits Under Power Bound Using Post-Silicon Operand Bitwidth Truncation

Increasing device parameter variations in nanometer CMOS technologies cause large spread in circuit parameters such as delay and power, leading to parametric yield loss. For digital signal processing (DSP) hardware, variations in circuit parameters can significantly affect the quality of service (QoS). Existing post-silicon calibration and repair approaches rely on adaptation of circuit operating parameters such as voltage, frequency, or body bias and typically incur large delay or power overhead. This paper presents a novel low-overhead approach of healing DSP chips by commensurately truncating the operand width based on their process shifts. The proposed approach exploits the fact that critical timing paths in typical DSP datapaths originate from the least significant bits. Hence, truncation of these bits, by setting them at constant values, can effectively reduce the delay of a unit, thereby avoiding delay failures. The proposed technique is applied to two common DSP blocks, namely discrete cosine transform (DCT) and finite impulse response (FIR) filter. Simulation results show significant reduction in critical path delay along with a graceful degradation in the QoS. They also show large improvement in manufacturing yield (41.6%) with up to 5X savings in power compared to existing approaches such as voltage scaling and body biasing.

A statistical yield optimization framework for interconnect in double patterning lithography

In double patterning lithography, within-layer overlay error results in critical dimensions variability. Overlay error has been considered as a systematic source of variation; however, it is segueing into a random error for technology nodes smaller than 45-nm. Therefore, statistical design techniques should be applied to estimate and optimize the yield loss due to overlay error. In this paper, we study the impacts of overlay error on functional and parametric yields of interconnects in 32- and 22-nm technologies. A yield optimization method is applied to derive optimal width and spacing of interconnects for mentioned technologies. Experimental results show that parametric yield loss becomes more problematic in 22-nm technology node compared with the functional yield loss. Moreover, we show that DFM techniques such as wire spreading are necessary to realize the desirable parametric constraints in 22-nm node. Our analysis reveals that overlay electrical impact increases considerably in DPL in the presence of congestion.

Evaluation of Analog/RF Test Measurements at the Design Stage

We present a method that is capable of handling process variations to evaluate analog/RF test measurements at the design stage. The method can readily be used to estimate test metrics, such as parametric test escape and yield loss, with parts per million accuracy, and to fix test limits that satisfy specific tradeoffs between test metrics of interest. Furthermore, it provides a general framework to compare alternative test solutions that are continuously being proposed toward reducing the high cost of specification-based tests. The key idea of the method is to build a statistical model of the circuit under test and the test measurements using nonparametric density estimation. Thereafter, the statistical model can be simulated very fast to generate an arbitrarily large volume of new data. The method is demonstrated for a previously proposed built-in self-test measurement for low-noise amplifiers. The result indicates that the new synthetic data have the exact same structure of data generated by a computationally intensive brute-force Monte Carlo circuit simulation.

New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits

Estimation of asynchronous circuit performances, such as speed, is one of the major reasons that still keeps that design style undeservedly unpopular. A simple logic simulator would be very useful in overcoming this problem if it is used for evaluating the worst-case delays in the paths of an asynchronous circuit using. In this paper a method for timing analysis of the asynchronous circuits using a VHDL simulator is presented. It is capable to deal with both non-sequential and sequential asynchronous circuit. An appropriate extension of the standard logic simulation process enables all worst-case delays for all paths in a digital circuit to be obtained with only one run of the simulation. High levels of accuracy are achieved using extensive gate modelling while statistical analysis of the results was also used to evaluate part of the parametric yield loss related to the delay. Due to the lack of asynchronous benchmark circuits, the method is verified on a set of asynchronous circuit selected by the authors.

A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance

Increasing levels of process variation in current technologies have a major impact on power and performance and result in parametric yield loss. In this paper, we develop an efficient gate-level approach to accurately estimate and optimize the parametric yield, defined by leakage power and delay limits, by finding their joint probability distribution function. We consider inter-die variations, as well as intra-die variations, with correlated and random components. The correlation between power and performance arises due to their dependence on common process parameters and is shown to have a significant impact on the yield, particularly in high-frequency bins. We then propose a new heuristic approach to incrementally compute the gradient of yield with respect to gate sizing and gate-length biasing in the circuit with high efficiency and accuracy. We show how this gradient information can be effectively used by a nonlinear optimizer to perform yield optimization. The proposed yield-analysis approach is compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%. The proposed optimization approach is implemented and tested, and we demonstrate an average yield increase of 40% using gate sizing (as compared to a deterministically optimized circuit). Even higher improvements are demonstrated when both gate sizing and gate-length-biasing techniques are used.

Defect spatial pattern recognition using a hybrid SOM–SVM approach in semiconductor manufacturing

As manufacturing geometries continue to shrink and circuit performance increases, fast fault detection and semiconductor yield improvement is of increasing concern. Circuits must be controlled to reduce parametric yield loss, and the resulting circuits tested to guarantee that they meet specifications. In this paper, a hybrid approach that integrates the Self-Organizing Map and Support Vector Machine for wafer bin map classification is proposed. The log odds ratio test is employed as a spatial clustering measurement preprocessor to distinguish between the systematic and random wafer bin map distribution. After the smoothing step is performed on the wafer bin map, features such as co-occurrence matrix and moment invariants are extracted. The wafer bin maps are then clustered with the Self-Organizing Map using the aforementioned features. The Support Vector Machine is then applied to classify the wafer bin maps to identify the manufacturing defects. The proposed method can transform a large number of wafer bin maps into a small group of specific failure patterns and thus shorten the time and scope for troubleshooting to yield improvement. Real data on over 3000 wafers were applied to the proposed approach. The experimental results show that our approach can obtain over 90% classification accuracy and outperform back-propagation neural network.

A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits

Variability in process parameters leads to a significant parametric yield loss of high-performance ICs due to the large spread in leakage-power consumption and speed of chips. In this paper, we propose an algorithm for total power minimization under timing constraints in the presence of variability. The algorithm is formulated as a robust optimization program with a guarantee of power and timing yields, with both power and timing metrics being treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold-voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. The performance of the algorithm was evaluated on a variety of public and industrial benchmarks, with a library characterized using 70-nm Berkeley Predictive Technology Model. When compared to the deterministic optimization, the new algorithm, on average, reduces static power and total power at the 99.9th quantile by 31% and 17%, respectively, without loss of parametric yield. The run-time on the benchmarks is 30times faster than other known statistical power-minimization algorithms.

Parametric Yield Analysis and Optimization in Leakage Dominated Technologies

Parametric yield loss has become a serious concern in nanometer technologies. In this paper, we propose a methodology to estimate and optimize the parametric yield of a design in the presence of process variations. We discuss the impact of leakage on parametric yield given that leakage causes the parametric yield window to shrink by imposing a two-sided constraint in conjunction with performance targets on the yield window. We present a mathematical framework for yield estimation under process variation for a given power and frequency constraints. The model is validated against Monte Carlo SPICE simulations in a 90-nm CMOS process and is shown to have a typical error of less than 5%. We then demonstrate the importance of optimal supply and threshold voltage selection for yield maximization. Our results show that parametric yield is highly sensitive to supply voltage with only a 5% change in the supply voltage potentially leading to nearly 15% yield degradation. We also investigate the sensitivity of parametric yield to required frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.

Relation between yield and reliability of integrated circuits and application to failure rate assessment and reduction in the one digit FIT and PPM reliability ERA

Clear relations have been established between E-sort yield and burn-in, EFR and field failure rates for nearly 50 million high volume products in bipolar, CMOS and BICMOS technologies from different waferfabs. The correlations obey a simple model that assumes that the reliability defect density is a fraction of the waferfab defect density and that rootcauses of failures are the same. The model allows a die size independent prediction and assessment of FIT and PPM reliability levels of an IC just based on its yield, eliminating the need for excessive lifetesting. ‘Maverick’ batches are identified by more than 2 to 3 rejects per batch and can not be eliminated by scrap of low yielding wafers alone. For non-mature technologies only correlations with functional yield are found, the parametric yield loss can be disregarded. Using the results, it is shown how reliability can be improved in a fast and controlled way, even in the 1 digit FIT and PPM reliability era, by reducing waferfab defect density, elimination of special causes and implementation of screens at product test like voltage screen and Iddq testing. As the effect of yield on PPM reject level is not that strong, the latter approach can be very effective in improving reliability.

A unified yield model incorporating both defect and parametric effects

A new approach to modeling yield is presented, which inherently includes both the effects of the conventional defect contributors and the parametric yield loss contributors often treated separately in existing yield models. These parametric yield losses are particularly important during the startup yield-improvement phase of new technology introduction, in many performance-sensitive products such as analog devices and high-speed digital devices, and in analyses of bin-split yields. By assuming a distribution in the size of defects, from point defects up to defects as large as or larger than a wafer, the parametric yield contributors can be viewed as simply rather large, design-dependent defects, which will render IC's unacceptable if any portion of the large defect overlaps the defect-sensitive area of a chip. In this way, the conventional Poisson model, or various extensions of the well-known Murphy model, can be augmented in a straightforward and general way to include parametric yield loss. It is shown that parametric yield losses introduce an additional die size dependence for yield that can help to account for the observed dependence of yield on die area. The model is compared to other models and to experimental yield data to illustrate both its utility in separating yield contributors and its close agreement with experimental yield data.

Use of short-loop electrical measurements for yield improvement

Modern submicron processes are more sensitive to both random and systematic wafer-level process variation than ever before. Given the dimensional control limitations of new technologies, the amount of wafer-to-wafer and within wafer nonuniformity of many steps is becoming a significant fraction of the total error budget, which already includes the usual step-to-step allocations. However, a significant portion of the total observed variability is systematic in nature. Accordingly, particle defects may not continue to dominate parametric yield loss without improved understanding of parametric variations. In this paper, we demonstrate the use of short-loop electrical metrology to carefully characterize and decouple wafer-level variability of several critical processing steps. More specifically, we present our method and give results obtained from variability analyses for lithography critical dimension (CD) and inter-level dielectric (ILD) thickness control. Using statistically designed experiments and dedicated test structures, the main factors affecting dielectric thickness variability has been identified. The systematic variability from a wafer stepper has been extracted using a physically based statistical data filter. Once isolated, the deterministic variability can be modeled and controlled to enhance process and circuit design for manufacturability (DFM). We hope that in the future this work will be coupled with novel DFM-oriented CAD tools that encapsulate this information in a fashion that makes it useful to process and circuit designers. >

OPTIMIZATION OF PARAMETRIC YIELD: A TUTORIAL

Yield loss can be characterized as either catastrophic or parametric. Catastrophic yield loss is primarily due to local disturbances, such as spot defects, that occur in a manufacturing process. On the other hand, parametric yield loss is due to global disturbances, such as mask misalignment. In this paper we briefly explore these two different types of yield loss and then review some methods that have been developed to maximize parametric yield.