A statistical yield optimization framework for interconnect in double patterning lithography

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In double patterning lithography, within-layer overlay error results in critical dimensions variability. Overlay error has been considered as a systematic source of variation; however, it is segueing into a random error for technology nodes smaller than 45-nm. Therefore, statistical design techniques should be applied to estimate and optimize the yield loss due to overlay error. In this paper, we study the impacts of overlay error on functional and parametric yields of interconnects in 32- and 22-nm technologies. A yield optimization method is applied to derive optimal width and spacing of interconnects for mentioned technologies. Experimental results show that parametric yield loss becomes more problematic in 22-nm technology node compared with the functional yield loss. Moreover, we show that DFM techniques such as wire spreading are necessary to realize the desirable parametric constraints in 22-nm node. Our analysis reveals that overlay electrical impact increases considerably in DPL in the presence of congestion.