Parameters Of Semiconductor Devices Research Articles

Addressing challenges inverse problem with convolutional neural networks and regulation techniques: Applications in extraction of physical parameters of semiconductors devices

The instability of the inverse problem is caused by its nonlocal and non-causal nature. This study addresses the inverse problem of determining the physical parameters of semiconductor devices. Based on statistical inversion theory, the probability distribution (posterior distribution) of the SBHs has been estimated by convolutional neural networks. Regularization techniques were then applied to such a distribution to accurately determine the SBHs of semiconductor devices. The results reveal that the fluctuations in the predicted SBHs by convolutional neural networks are similar to the amplitude between the upper and lower envelopes of the free decay curve. The method achieves a maximum relative error below 3.4% when using theoretical diode current–voltage data as input and maintains a relative error of less than 7% when compared to traditional methods when using experimental current–voltage data. Furthermore, the proposed method offers a mathematical interpretation of the inverse problem and demonstrates the capability of the proposed method to extract the physical parameters of semiconductor devices with a small amount of data.

Set-Up for Measuring Thermal Parameters of Power Semiconductor Devices

In order to determine the junction temperature of semiconductor devices operating at different power supply and cooling conditions, their thermal parameters are needed. This article describes an original measurement set-up enabling the determination of thermal parameters of power semiconductor devices. In contrast to other set-ups described in the literature, this set-up makes it possible to measure thermal parameters which characterize the efficiency of the removal generated due to a self-heating phenomenon, as well as the parameters characterizing mutual thermal couplings. The presented set-up makes use of an indirect electrical method to determine the junction temperature of diodes, bipolar and unipolar transistors and IGBTs. The methods used to measure the self and transfer transient thermal impedances of these devices and the construction of the set-up are described. The influence of selected factors on the accuracy of the measurements is analyzed. Examples of the measurement results of thermal parameters (self and transfer transient thermal impedances) of power semiconductor devices operating at different cooling conditions are presented. The obtained research results are discussed.

(Invited) Heterogeneous Integration of Ultrawide Bandgap III-Nitrides and Diamond

Industry demands for power switching, amplification and photonic applications are continually pushing the limits of semiconductor device technologies leading to increasing applied voltages and, thus, higher electric fields while simultaneously requiring reduction in the size, weight and power consumption. In addition, recent heightened interest in higher temperature (and other extreme environment) applications, while simultaneously maintaining high-voltage and high-power performance, has inexorably led to ultrawide bandgap (UWBG) semiconductor materials. This interest in UWBG materials stems from superior properties that include high material hardness, breakdown strength to withstand large electric fields and mitigation of power dissipation during device switching, deliver high current density while operating at higher junction and ambient temperature. Among these materials are boron nitride in its hexagonal and cubic phases, gallium oxide, diamond, and aluminum gallium nitride. The versatile alloys of wurtzite AlxGa1-xN have long been demonstrated across the full composition range. The variation in Eg with AlGaN composition, along with select WBG and UWBG materials, is shown in Figure 1 versus (in-plane for non-cubic) lattice constant.Premier WBG materials to date for electronics and photonics are SiC (Eg = 3.3 eV) and GaN (Eg = 3.4 eV). The latter has been successfully applied to high-power transistors and near ultraviolet photonics. In both electronics and photonics applications, the polarization fields of the wurtzite crystal structure, generally grown along (0001) direction, produce design challenges. In photonics, for example, the fields and band alignment couple to spatially separate electrically injected electrons and holes to reduce wavefunction overlap in quantum wells. In electronics, the internal fields have contributed to difficulties in the design of logic and bipolar transistor devices based on these materials. Despite this, the inherent polarization field and band offsets were successfully employed in the design of high electron-mobility transistors (HEMTs). The inherent AlGaN/GaN HEMT band offset produces a high electron concentration at the interface that spontaneously forms a two-dimensional electron gas (2DEG). Because charge flow in these devices is restricted to the 2DEG, current crowding results in intense self-heating. The local heating decreases electrical conductivity to produce a runaway scenario for elevating the Joule heating. Dissipating this heat, therefore, is the principal limiting factor in operating at power higher than 40 W/mm.The various temperature dependences of semiconductor device parameters are the principal drivers in the operation of semiconductor devices. The physics has inextricably led to UWBGs for future high temperature applications, > 300 °C, due to their lower intrinsic carrier density and thus the effects of leakage are orders of magnitudes less than Si-based devices. Furthermore, AlGaN and diamond offer superior high temperature mechanical stability due to their structural hardness and chemical inertness. Thermal management is essential for achieving higher power densities. Diamond is highly attractive for many applications due to its high hardness, transparency, chemical inertness, promising semiconductor properties, and its high thermal conductivity (κ) to 2500 W/m·K in natural material. Factors related to the consequences of self-heating in devices have motivated extensive research to improve the properties of diamond and produce better approaches to determine the thermal properties. Laboratory-grown diamond films exhibit significantly poorer κ than natural diamond and, when integrated with other electronic materials, a low thermal boundary conductance (TBC in W/m2·K) that inhibits heat transfer between materials. The former originates from the ubiquitous polycrystalline nature of chemical vapor deposition (CVD) diamond and the presence of non-diamond carbon (NDC) in the layer. The low TBC stems from fundamental barriers to phonon propagation between two materials and from practical issues of poor diamond quality in the initial growth regime. Continued research is needed to improve κ in the polycrystalline diamond and mitigate the negative impact of the initial diamond layer on TBC.The current status of hetero-integration of UWBG AlGaN and diamond will be reviewed. Particular emphasis is given to high Al content AlGaN for near-bandgap matching with diamond. Patterned diamond grown using hot-filament CVD to realize unique three-dimensional lateral device structures in a self-aligned, as-grown fabrication process is employed. Engineering the AlGaN-diamond bandgap alignment is noteworthy at the nonpolar AlGaN – diamond interface including diamond surface terminations that produce either negative or positive electron affinity. The review will focus on improvements in material properties, especially the interfaces, that are critical to both charge and heat transport for UWBG device structures. Figure 1

On the Problems of Current Limitations in Networks Based on Power Semiconductor Devices

The presence of high short-circuit currents (200–300 kA) in autonomous and generator power systems of low and medium voltage classes, causing a decrease in the switching resource of switching facilities, necessitates the search for ways of limiting the current. The paper proposes a solution to this problem: a semiconductor current-limiting device based on a DC chopper, a DC-to-DC converter. This devices’ features are its low dimensions and losses during typical operation. Semiconductor elements can be arranged quite compactly due to the lack of radiators for cooling, since the cooling process—taking into account the short duration of the current limitation process—is not efficient. The choice of semiconductor devices takes into account the short duration of the current load, as a result of which the temperature of the semiconductor structure does not exceed its permissible value. This paper presents a method for calculating the parameters of semiconductor devices, taking into account the current load as well as adjusting the magnitude of current limitation to a value that can be disconnected by switching devices. The short-term mode of operation of the power semiconductor device with current regulated by the frequency and duty cycle of its operation makes it possible to facilitate the required current limitation in the circuit for the subsequent fault clearance with a typical electrical device. The problem of overcurrent of one of the elements of the limiter is noted, which requires special attention to ensure that the semiconductor device is not overheated. This paper also presents the principle of current limitation, summarizes the results of experimental studies, and analyzes the presented capabilities of a semiconductor current limiter.

Preliminary Study on Automatic Detection of Hard Defects in Integrated Circuits Based on Thermal Laser Stimulation

Locating the fault position is a crucial part of the failure mechanism analysis of integrated circuits. This paper proposes a hard defect locating system based on Thermal Laser Stimulation (TLS) technology. The equation for laser-induced changes in the electrical parameters of semiconductor devices is a good guide to the hardware and software design of the hard defect locating system. The scanning mode of fast total scanning combined with slow point-to-point scanning can quickly locate abnormal areas. A modified median absolute difference (MAD) method is applied to the extraction of anomalous data. The system software can automatically and collaboratively control the 3D mobile station, laser, and signal acquisition unit. It also can intuitively display the distribution of abnormal points on the infrared image. Using a failure MRAM chip and a good one to conduct a comparative test, the abnormal points distributed on the infrared image of the chip indicate that the failure area is in the digital module or eFuse module of the chip, and the Emission Microscopy (EMMI) experiment also verifies the accuracy of the test system.

Quality control of lifetime drift effects

Electrical parameters of semiconductor devices are specified in their product data sheets. These parameters have to stay within their specified ranges over lifetime. The lifetimes of semiconductor devices are simulated by accelerated stress tests. In the course of these stress tests, electrical parameters are checked for any change in their values. This change can occur at semiconductor devices and is called lifetime drift. In order to avoid that electrical parameters drift out of their specified limits, the devices are tested with tighter limits at the end of the production line. These limits are referred to as test limits. The differences between test limits and specification limits are called guard bands. Guard bands are optimized to reduce yield losses and ensure compliance with the product data sheets over lifetime.In this paper, a simplified lifetime drift model for continuous electrical parameters is introduced. The drift calculation is faster compared to existing models, requires less memory resources, and is suitable for edge devices. It is tailored to the needs of semiconductor manufacturers and their development and production flows. It considers additional information on the stress test data. With this model, one can detect and quantify lifetime drift, calculate typical drift patterns, and optimize guard bands based on quality targets. Thus, this model enables fast, efficient, and accurate calculations of test limits.

Implementation of Fast Measurement System of Semiconductor Device Parameter Temperature Coefficient Based on FPGA

In this paper, a fast temperature coefficient measurement system based on FPGA is presented to rapidly measure the temperature coefficient of semiconductor device parameters. The design methods of hardware circuit, software system and FPGA program are put forward here. The system uses the heating platform to linearly raise the temperature of the device, and collects the voltage and temperature information in real time. Through the integration and processing of a large number of data, the temperature coefficient of DUT can be obtained rapidly and accurately. Based on this system, the silicon-based Schottky barrier diode (Si SBD) is studied, and the diode temperature coefficient is obtained. Compared with the steady-state method to verify the rapidity, accuracy and efficiency of the system. It can be used in the field of electrical and thermal measurement of semiconductor devices.

Adaptive algorithms for measuring low-frequency noise parameters of semiconductor devices under mass control

The solution of the problem of increasing the confidence and efficiency of quality control of semiconductor devices is considered. The analysis of conditions for measuring the power spectral density of low – frequency noise of semiconductor devices with a spectrum of the form (γ – the spectrum shape indicator) under mass quality control is presented. The error in measuring the power spectral density under the specified measurement conditions strongly depends on the value of the spectrum shape indicator. Adaptive algorithms for measuring low-frequency noise parameters are proposed for cases of a given limit error in measuring the power spectral density and a given time for a single measurement. The proposed algorithms include a preliminary estimation of the value of the spectrum shape indicator and subsequent measurement of the noise power spectral density at the optimal filter bandwidth. The optimal filter bandwidth is determined based on the results of a preliminary assessment of the spectrum shape indicator. For both cases, we obtained estimates of the gain in the sense of the average for the set (ensemble) of controlled products. The possibility of adaptive or cognitive adjustment of the measurement system parameters in the control process based on the results of evaluating sample averages in the training sample is discussed.

Estimation of the impact of semiconductor device parameters on the accuracy of separating a mixed production batch

In this paper, we investigate the problem of separation of a mixed production batch of semiconductor devices for the space industry into homogeneous production batches. The method of factor analysis is applied to reduce the dimensionality of the problem. We investigate the impact of measured parameters of semiconductor devices in the accuracy of the separation of the mixed lot, composed several homogeneous batches. It was shown, that with any orthogonal rotations of factor structure as the number of homogeneous batches in the sample increases, the clustering accuracy reduces. Groups of semiconductor device parameters which have the greatest impact on the partition accuracy regardless of the number of homogeneous batches in the sample detected.

Increase of accuracy of capacitance parameters measurements of power semiconductor modules on base IGBT and FRD

This investigation presents an overview of questions related to the increase in accuracy of measurements of capacitance parameters of power semiconductor modules when developing a device for automated measurements. Result addresses the matters of circuit engineering of primary components, technical characteristics and software of a meter designed to automate the process of testing of capacitance parameters of power modules based on IGBT (insulated gate bipolar transistors) and FRD (fast recovery diodes). Unit testing results that prove the efficiency of the proposed method of the technical implementation are studied. Software implementation is described; ways to improve software-hardware solution are proposed. The obtained results can be used for automated testing of electric parameters of power semiconductor devices.

Colloidal Synthesized Cobalt Nanoparticles for Nonvolatile Memory Device Application

Colloidal synthesized metal nanoparticles (NPs) have great potential to be utilized as economically viable and efficient charge storage floating gate for the non-volatile memory (NVM). Present research work focuses on the NVM device application of colloidal synthesized cobalt (Co) NPs using simple spin coating process. The metal-oxide-semiconductor (MOS) NVM capacitor devices with and without Co-NPs of average size of 5 nm have been fabricated. The MOS NVM and control devices have tunnel oxide (SiO2) thickness of 3.9 nm grown using rapid thermal processing and control dielectric (Al2O3) thickness of 10 nm deposited using atomic layer deposition. Colloidal synthesized Cobalt (Co) NPs deposition over silicon dioxide wafer has been done using optimized spin coating process. Electrical characterization of fabricated devices has been done using proxima B1500 semiconductor device parameter analyzer. Capacitance-voltage (C-V) characteristics of fabricated MOS NVM device shows a large flat band voltage shift ( $\Delta {V}_{{fb}}$ ) of around 8.00 V after applying a sweep voltage of −6 V to +6 V and then +6 V to −6 V in C-V response curves. Where, the control device shows negligible $\Delta {V}_{fb}$ in comparison to MOS NVM device. The program and erase characteristics of the fabricated device have also been studied by Fowler–Nordheim tunneling, resulting in 2.31-V memory window for program/erase pulse of ±5 V. The retention capability has been studied by capacitance versus time (C-t) characteristics. This shows a fairly steady C-t response, indicating strong retention capability of fabricated device.

An Analysis of the Highly Linear Transfer Characteristics of Dual-Buck Converters

Practical switching devices have finite turn-on and turn-off times. To avoid short circuit, a blanking time is added between turn-off and turn-on of the complementary working switches in a switching-leg. The blanking time, also referred to as deadtime, is one of the dominant sources of output current and voltage distortion in pulse-width modulated (PWM) power amplifiers. Extensive studies exist on elimination, minimization, and compensation of the effect. Most techniques achieve a reduction of the distortion but are not capable of completely removing it. The dual-buck (DB) converter does not suffer from blanking-time-related distortion. However, blanking time is not the only source of switching-leg-induced distortion. This paper focuses on the effects of semiconductor device parameters on the output quality of the DB converter. It is shown that, ideally, the forward voltages of the diodes and switches have no effect on the output quality. Measurements on a prototype, industrial power stack based, DB converter show a 100 times improvement of the open-loop spurious free dynamic range when compared to conventional PWM converters.

Sensitivity of Breakdown Voltage of Power Transistors to Dopant Impurities

The doping sensitivity functions provide a powerful tool to analyze the effects of doping variations on the parameters of power semiconductor devices. They can be coupled with gradient-based optimization algorithms to design the doping profiles in power devices and are instrumental in the statistical analysis of these devices. In this article we discuss about applications of the doping sensitivity functions in power devices. We focus mostly on maximizing the breakdown voltage and minimizing the on-state resistance and on the numerical evaluation of the acceptor and donor sensitivity functions of the breakdown voltage. Simulation results are presented and analyzed for a standard insulated gate bipolar transistor.

Modern methods and means for nondestructive testing of the quality of power semiconductor devices

Modern methods and means for designing devices for nondestructive testing of parameters of power semiconductor devices are described. A new method for determining the junction–case thermal resistance from the transition function of a thermosensitive parameter is presented. The operating principle of a specialized digital system for controlling and displaying the vibration frequency and linear accelerations during testing of the absence of freely moving particles, short circuits, and breaks in the circuits of electrodes is presented. The function of digital filtering of a signal that is formed by the sensor–accelerometer board is considered. A new method for the formation of a single shock-current pulse is described that is based on the use of the principle of a discrete superposition of charges in the electric circuit of the secondary winding of a power pulse transformer. The principle of the formation of a test voltage pulse in a test-pulse generator of the software–hardware complex for the automatic assignment of grades, which is based on the implementation of the pulse-amplitude modulation of pulse parameters in a galvanically isolated power control loop, is presented.

Ultra-Small ZnO Nanoparticles for Charge Storage in MOS-Memory Devices

Recently, there has been a growing scientific and technological interest in the II-VI compound semiconductor ZnO. This is due to the wide-ranging applicable properties of ZnO such as high electron mobility, high transparency, piezoelectricity, large direct band gap around 3.4 eV, in addition to luminescence due to its large exciton binding energy (around 60 meV) [1, 2]. Furthermore, fabricating ZnO nanostructures with different dimensions in the nanometer range allow tuning of the ZnO properties due to quantum confinement effects [3,4]. In this work, 1 to 5 nm ZnO nanoparticles are characterized and studied for MOS memory application. The ZnO nanoparticles (NPs) are first characterized by dip coating a quartz wafer in the solution which contains ZnO nanoparticles stabilized by polyacrylate sodium. Amplitude Modulation-Atomic force microscopy (AM-AFM) measurements are conducted on the sample and the height map (depicted in Fig. 1) shows that the majority of the ZnO nanoparticles have an average height of 1.8 nm and a width > 15-nm. This means that there is a single layer of NPs which are agglomerated in the horizontal direction only. It has been reported that some nanoparticles agglomerations cause a change in the properties of the nanomaterials [5]. In this case, since the thickness of the agglomerations is in the range of the bohr radius of the ZnO exciton (~2.3 nm) [6], 2-D quantum confinement effects are expected to occur in the agglomerations. The reflectance and transmittance spectra are measured using a UV-Vis-NIR spectroscopy. The Kubelka-Munk function is used to extract the bandgap of the agglomerations, and the extracted value is 3.7 eV which is larger than the ZnO bulk bandgap (3.4 eV). The result is consistent with the 2-D quantum confinement effects. Then, MOS-memory devices are fabricated on an n+-type (111) (Antimony doped, 15-20 mΩ-cm) Si wafer. 4-nm tunnel oxide Al2O3 is deposited at 300°C in an Oxford FlexAL system. Then, the ZnO NPs are dip-coated on the sample. Next, 9-nm blocking oxide Al2O3 is deposited by plasma assisted ALD at 200°C. Finally, a 350-nm Al layer for the gate contact is e-beam evaporated using a shadow mask with feature size down to 10 μm which eliminated the need for any lithography steps. A cross-sectional illustration of the fabricated MOS-memory device is shown in Fig. 2. The electrical characterization of the fabricated memory devices is conducted by measuring the C-Vgate characteristics of the programmed and erased states at 1 MHz using the Agilent-B1505A Semiconductor Device Parameter Analyzer. The memory cells gate voltage (Vg) was first swept from -10 V forward to 10 V then backwards. An 8.2 V threshold voltage (Vt) shift is measured as shown in Fig. 3. The C-V measurements are repeated at different gate sweeping voltages as shown in Fig. 4. The curve shows that the ZnO-NPs are providing high density charge trapping states in the 2-D quantum well, and a large memory window of 4 V is obtained at a low program/erase voltage of 7/-7 V. The charge emission-mechanism during the program-operation is also studied. The natural-logarithm of the Vt shift divided by the square of the electric field across the tunnel oxide (Eox) is plotted vs. the reciprocal of Eox as depicted in Fig. 5. The linear trend indicates that the prevailing charge emission-mechanism at a Vg > 5 V (corresponding to Eox=5.01 MV/cm) is Fowler-Nordheim tunneling (F-N). In F-N tunneling, the charges are emitted by first tunneling into the conduction/valence band of the oxide through a triangular energy barrier and then are swept into the charge trapping layer by the electric field. Also, the linear trend observed in Fig. 6 which depicts the Vt shift vs. the square of Eox indicates that Phonon-Assisted Tunneling is the dominant charge emission-mechanism at Vg < 5 V. Finally, the results also show that the electric field across the tunnel oxide dictates the charge emission mechanism and therefore the operating voltage of the memory. The results also confirm that ZnO nanoparticles are promising in future nano-memory applications. This work was supported by Masdar Institute of Science and Technology. N. El-Atab acknowledges financial support provided by L’Oréal-UNESCO For Women in Science Middle East Fellowship. [1] U. Özgür, et al., J. Appl. Phys. 98, 041301, 2005, [2] N. El-Atab, et al., Appl. Phys. Lett. 104, 013112, 2014. [3] N. El-Atab et al., Appl. Phys. Lett. 104, 253106, 2014. [4] N. El-Atab et al., Appl. Phys. Lett. 105, 033102, 2014. [5] P. Francis et al., The European Physical Journal D, 67(7), 1-7, 2013. [6] Y. Gu et al., Appl. Phys. Lett., 85, 3833, 2004. Figure 1

Graphene Nanoplatelets Embedded in HfO2 for Mos Memory

Novel materials are being explored as charge storage media of MOS charge trapping memories to enhance their charge retention characteristic and lower their required operating voltage [1-5]. In this work, graphene nanoplatelets embedded in an ultrathin 1-nm HfO2 layer are investigated for charge storage in charge trapping MOS memory devices. The memory window achieved at different gate voltages and the energy band diagram of the memory structure are studied. The fabrication of the memory cells is conducted as follows: first a 5-nm-thick tunnel oxide Al2O3 is deposited at 250°C in Cambridge Nanotech Savannah-100 atomic layer deposition (ALD) system on an n+-type (111) (Antimony doped, 15-20 mΩ-cm) Si wafer. Next, 1-nm-thick HfO2 is deposited by Plasma Assisted ALD at 195°C in an Oxford FlexAL system. Then, the sample is placed on a hot plate at 110°C and 2-2.5 ml of graphene nanoplatelets solution with 0.05 mg/ml concentration are drop casted slowly using pipettes. A 1-nm-thick HfO2 is again deposited by plasma assisted ALD at 195°C followed by an 8-nm-thick Al2O3 blocking oxide deposited by ALD at 250°C. Finally, the gate contacts are created by e-beam evaporating a 400-nm-thick Al layer using a shadow mask with 10 μm feature size. An illustrative cross-section of the fabricated memory is shown in Fig. 1. In order to analyze the effect of embedding graphene nanoplatelets in the MOS memory and to quantify the stored charge at different gate voltages, high frequency (1MHz) C-Vgate measurements are conducted using an Agilent B1505A Semiconductor Device Parameter Analyzer to measure the programmed and erased characteristics of the fabricated memory devices as depicted in Fig. 2. The memory cells showed a 1.35 V threshold voltage (Vt) shift upon sweeping the gate voltage from -5 V forward to 5 V then backwards. At -7/7 V gate sweeping voltage, more charging is observed through the higher 3 V Vt shift. The results show that the memory is being programmed by storing electrons in the graphene nanoplatelets as shown by the shift of the programmed state in the positive direction at higher gate sweeping voltages. At 7/-7 V gate sweeping voltage and with a 3 V Vt shift, the charge trapping density in the graphene nanoplatelets is calculated [4] and found to be 1.54 ×1013 cm-3. Using the reported band offsets and band gaps of Al2O3, HfO2, and graphene, the energy band diagram of the memory is constructed as shown in Fig. 3 [6]. The conduction band offset between Si and tunnel oxide is smaller than the valence band offset (ΔEC = 2.44 eV < ΔEV = 3.24 eV), thus the electrons tunneling probability is expected to be higher which confirms the observed electrons storage. In addition, due to the large work-function of graphene, a deep quantum well is formed where electrons can be stored. In fact, the conduction band offset between charge trapping layer and tunnel oxide is very large (ΔEC = 2.99 eV) which exponentially reduces the leakage of stored electrons in the graphene nanoplatelets. Moreover, the addition of the high-dielectric constant (қ=20) HfO2 layer is expected to further reduce the leakage of stored charges. Finally, the results presented in this work indicate that graphene has potential in future low-power charge trapping memory devices. Acknowledgment: This work was supported by ATIC, and TUBITAK Grants 111A015, 112M004, 112E052 and 113M815. A.K.O. acknowledges support from the Turkish Academy of Sciences Distinguished Young Scientist Award (TUBA GEBIP).

Charge Trapping Memory with 2.85-Nm Si-Nanoparticles Embedded in HfO2

Innovative means to reduce the operating voltage and increase the stored charge density in current non-volatile memory devices are imperative [1-5]. In this work, 2.85-nm Si nanoparticles (Si-NPs) embedded in an ultrathin HfO2 layer are investigated for charge storage in low-cost non-volatile charge trapping memory devices. The memory hysteresis at different gate voltages, the stored charge, and the energy band diagram of the memory structure are analyzed. The memory cells are fabricated on an n+-type (111) (Antimony doped, 15-20 mΩ-cm) Si wafer. 5-nm-thick tunnel oxide Al2O3 is deposited at 250°C in Cambridge Nanotech Savannah-100 atomic layer deposition (ALD) system. Then, 1-nm-thick HfO2 is deposited by Plasma Assisted ALD at 195°C in an Oxford FlexAL system. Next, 2.85-nm Si-NPs are spin coated on the sample [6]. Again, a 1-nm-thick HfO2 is deposited by plasma assisted ALD at 195°C. Finally, an 8-nm-thick Al2O3 blocking oxide is deposited by ALD at 250°C. A 400-nm-thick Al layer for the gate contact is e-beam evaporated using a shadow mask with 10 μm feature size which eliminated the need for lithography steps. A cross-sectional illustration of the fabricated memory device is depicted in Fig. 1. The fabricated memory devices are electrically characterized by measuring the high frequency (1 MHz) C-Vgate characteristics of the programmed and erased states. Using the Agilent B1505A Semiconductor Device Parameter Analyzer, the memory cells gate voltage was first swept from -6 V forward to 6 V then backwards. A 1.8 V threshold voltage (Vt) shift is observed. The C-V measurements are repeated at a gate sweeping voltage of 8/-8 V and both erased and programmed states shifted outwards as shown in Fig. 2 resulting in a 4.5 V memory window. This indicates that the charge trapping layer is storing mixed charges: electrons and holes, however, more charging is due to holes revealed by the greater shift of the erased state in the negative direction as shown in Fig. 2. Moreover, the Vt shift is measured at different gate sweeping voltages as sown in Fig. 3 and the charge trapping density in the Si-NPs is calculated [3] and found to be 2.32 ×1013 cm-3. The analysis of the energy band diagram shows that the conduction band offset between Si and tunnel oxide is smaller than the valence band offset (ΔEC = 2.44 eV < ΔEV = 3.24 eV), thus the electrons tunneling probability is expected to be higher. However, the conduction band offset between the 2.85-nm Si-NPs [7] and tunnel oxide is much smaller than the valence band offset (ΔEC = 1.29 eV << ΔEV = 3.77 eV). This means that stored electrons can tunnel back to the Si channel much easier than holes. This confirms the observed larger charging due to holes in Fig. 2. Moreover, the addition of the high-dielectric constant (қ=20) HfO2 layer is expected to reduce the leakage of stored charges. Finally, the fabrication of such memory structure is compatible with existing semiconductor processing thus has potential on low-cost integrated nanoscale memory applications. Acknowledgment: This work was supported by ATIC, and TUBITAK Grants 109E044, 112M004, 112E052 and 113M815.

Research of Probability Distribution of Semiconductor Test Parameter

The probability distribution of electrical characteristic parameters of semiconductor device is an important reference which is used to analyze the reliability and quality consistency of devices. These distributions are considered as normal distribution at home and abroad. This paper utilized mature GaAs MESFET low noise amplifier as analytic sample which is volume production and wide application, and used high-precision Agilent B1505A device analyzer to test main electrical characteristics of 408 samples. After the distribution generation of test results, the Skewness-Kurtosis method was used to analyze probability distributions of the results. At last, the conclusion of distribution of measuring parameter is non-normal distribution was educed.

Transparent Graphene Nanoplatelets for Charge Storage in Memory Devices

Recently, graphene has been considered as a promising material for future low cost electronics because of its noteworthy properties, such as high carrier mobility, large work-function, thermal conductivity, structural robustness and optical transparency [1]. In this work, transparent graphene nanoplatelets are investigated for charge storage layers in low-cost non-volatile charge trapping memory devices. The memory electrical characterization, retention and endurance characteristics, and charge emission mechanism are analyzed. The memory cells are fabricated on an n+-type (111) (Antimony doped, 15-20 mµÙ-cm) Si wafer. 10-nm-thick Al2O3 is deposited at 250°C in Cambridge Nanotech Savannah-100 atomic layer deposition (ALD) system. Pristine graphene nanoplatelets (NanoIntegris PureSheets Quattro grade) are deposited by drop-casting technique. Samples are placed on hot-plate at 110°C and 2-2.5 ml of 0.05 mg/ml graphene solution is drop-casted slowly by using plastic pipette and samples are left to dry for 5 minutes on hot-plate. Then a 5-nm-thick Al2O3 tunnel oxide is ALD deposited at 250°C. A 400-nm-thick Al layer for the gate contact is sputtered using a shadow mask. A cross-sectional illustration of the fabricated memory device is depicted in Fig. 1a).Then, the memory devices are electrically characterized by measuring the C-Vgate characteristics of the programmed and erased states at high frequency (1 MHz). Using the Agilent B1505A Semiconductor Device Parameter Analyzer, the memory cells gate voltage was first swept from -10 V forward to 10 V. The obtained C-V characteristic corresponds to the erased state as shown in Fig. 1b). Then, upon sweeping the gate voltage from +10 V to -10 V, there was a near parallel shift in the measured C-V curve in the positive direction as seen in Fig. 1b). The positive shift is due to electrons storage in the graphene nanoplatelets and the value of the Vt shift is 4.4 V. The Vt is extracted at a capacitance of 500 pF at the onset of the depletion region. The measured memory window at different operating voltages indicates a large Vt shift (3.6 V) at low operating voltages (8/-8 V). At 10/-10 V, the charge trap states density of the graphene is calculated and found to be 5.83×1012 cm-2 [2]. Furthermore, to identify the electron emission mechanism, the electric field across the tunnel oxide is calculated [3] and the natural logarithm of the Vt shift divided by the square of the electric field is plotted vs. the reciprocal of the electric field as shown in Fig. 2. In Fowler-Nordheim tunneling (F-N), the charges are injected by tunneling into the conduction band of the oxide through a triangular energy barrier and then are swept by the electric field into the charge trapping layer. The emission rate of charges in F-N tunneling is exponentially proportional to the reciprocal of the electric field times the electric field squared [3]. Thus, the linear trend presented in Fig. 2 indicates that the dominating electron emission mechanism at electric fields larger than 5.6MV/cm (corresponding to a gate voltage of 6V) is F-N tunneling. Finally, the fabrication of such graphene based memory structure is compatible with existing semiconductor processing thus has potential on low-cost integrated nanoscale memory applications. Acknowledgment: This work was supported by ATIC, and TUBITAK Grants 109E044, 112M004, 112E052 and 113M815. References N. El-Atab, A. Ozcan, S. Alkis, A. K. Okyay, and A. Nayfeh "Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission", Appl. Phys. Lett. 104, 013112 (2014).F. Schwierz, Graphene transistors. Nat. Nanotechnol. 5, 487–496 (2010).S. M. SZE, “Nonvolatile Memory Devices,” in Physics of Semiconductor Devices, 3rd ed. New Jersey: Wiley, 2007.

Characterization of Changes in LDO Susceptibility After Electrical Stress

The low dropout voltage regulator (LDO) is very sensitive to electromagnetic interference (EMI) coupled onto the power supply, with concomitant output voltage offset. Most electromagnetic compatibility analyses of the LDO do not account for the effects of ageing. However, device ageing can degrade the physical parameters of semiconductor devices and can worsen the effect of EMI. This paper analyses the drift in LDO immunity after accelerated ageing. A large number of measurements that show the variations in the test results for dc characteristic, impedance, and immunity reveal increasing susceptibility after electrical accelerated ageing.