Quality control of lifetime drift effects

Abstract

Electrical parameters of semiconductor devices are specified in their product data sheets. These parameters have to stay within their specified ranges over lifetime. The lifetimes of semiconductor devices are simulated by accelerated stress tests. In the course of these stress tests, electrical parameters are checked for any change in their values. This change can occur at semiconductor devices and is called lifetime drift. In order to avoid that electrical parameters drift out of their specified limits, the devices are tested with tighter limits at the end of the production line. These limits are referred to as test limits. The differences between test limits and specification limits are called guard bands. Guard bands are optimized to reduce yield losses and ensure compliance with the product data sheets over lifetime.In this paper, a simplified lifetime drift model for continuous electrical parameters is introduced. The drift calculation is faster compared to existing models, requires less memory resources, and is suitable for edge devices. It is tailored to the needs of semiconductor manufacturers and their development and production flows. It considers additional information on the stress test data. With this model, one can detect and quantify lifetime drift, calculate typical drift patterns, and optimize guard bands based on quality targets. Thus, this model enables fast, efficient, and accurate calculations of test limits.